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    參數(shù)資料
    型號: SL28548ALC-2T
    元件分類: 時鐘產(chǎn)生/分配
    英文描述: PROC SPECIFIC CLOCK GENERATOR, QCC64
    封裝: 9 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, QFN-64
    文件頁數(shù): 8/32頁
    文件大小: 685K
    代理商: SL28548ALC-2T
    SL28548-2
    Rev 1.5 July 28, 2008
    Page 16 of 32
    Byte 18: Control Register 18
    The SL28548-2 requires a Parallel Resonance Crystal. Substi-
    tuting a series resonance crystal causes the SL28548-2 to
    operate at the wrong frequency and violates the ppm specifi-
    cation. For most applications there is a 300-ppm frequency
    shift between series and parallel crystals due to incorrect
    loading
    Crystal Loading
    Crystal loading plays a critical role in achieving low ppm perfor-
    mance. To realize low ppm performance, use the total capac-
    itance the crystal sees to calculate the appropriate capacitive
    loading (CL).
    Figure 1 shows a typical crystal configuration using the two
    trim capacitors. It is important that the trim capacitors are in
    series with the crystal. It is not true that load capacitors are in
    parallel with the crystal and are approximately equal to the
    load capacitance of the crystal.
    Calculating Load Capacitors
    In addition to the standard external trim capacitors, consider
    the trace capacitance and pin capacitance to calculate the
    crystal loading correctly. Again, the capacitance on each side
    7
    0
    SMSW_EN
    Enable Smooth Switching
    0 = Disabled, 1= Enabled
    6
    0
    SMSW_SEL
    Smooth switch select
    0 = CPU_PLL, 1 = SRC_PLL
    5
    0
    SE1/SE2 _DSC0
    SE1 and SE2 drive strength Setting 2 of 3(see Byte 18 for more setting)
    0 = Low, 1= High
    4
    0
    Prog_PCI-E_EN
    Programmable PCI-E frequency enable
    0 = Disabled, 1= Enabled
    3
    0
    Prog_CPU_EN
    Programmable CPU frequency enable
    0 = Disabled, 1= Enabled
    2
    0
    REF_DSC0
    REFdrive strength strength Setting 2 of 3(see Byte 18 for more setting)
    0 = Low, 1= High
    1
    0
    USB_DSC0
    USB drive strength strength Setting 2 of 3(see Byte 18 for more setting)
    0 = Low, 1= High
    0
    PCI/ PCIF_DSC0
    PCI drive strength strength Setting 2 of 3(see Byte 18 for more setting)
    0 = Low, 1= High
    Byte 17: Control Register 17 (continued)
    7
    0
    REF_DSC2
    Drive Strength Control (DSC: 2:0)
    6
    0
    RESERVED
    5
    0
    RESERVED
    4
    0
    RESERVED
    3
    0
    USB_DSC2
    2
    0
    PCI/PCIF_DSC2
    1
    0
    SE1/SE2_DSC2
    0
    RESERVED
    DSC_2
    (Byte18)
    DSC_1
    (Vario us B ytes )
    DSC_0
    (Byte 17)
    Buf f er
    Strength
    1
    Strongest
    1
    0
    1
    0
    1
    0
    1
    Def ault
    0
    1
    0
    1
    0
    Weakest
    Table 5. Crystal Recommendations
    Frequency
    (Fund)
    Cut
    Loading Load Cap
    Drive
    (max.)
    Shunt Cap
    (max.)
    Motional
    (max.)
    Tolerance
    (max.)
    Stability
    (max.)
    Aging
    (max.)
    14.31818 MHz
    AT
    Parallel
    20 pF
    0.1 mW
    5 pF
    0.016 pF
    35 ppm
    30 ppm
    5 ppm
    Figure 1. Crystal Capacitive Clarification
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