參數(shù)資料
型號: SL28548ALC-2T
元件分類: 時鐘產(chǎn)生/分配
英文描述: PROC SPECIFIC CLOCK GENERATOR, QCC64
封裝: 9 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, QFN-64
文件頁數(shù): 28/32頁
文件大?。?/td> 685K
代理商: SL28548ALC-2T
SL28548-2
Rev 1.5 July 28, 2008
Page 5 of 32
51
SRCT7/ CR#_F
I/O,
DIF
True 100 MHz differential serial reference clocks/3.3V CR#_F Input.
Selected via CR#_E_EN/CR#_F_EN bit located in byte 6 bit 7 and 6.
When selected, CR#_E controls SRC6, CR#_F controls SRC8
52
VDD_SRC_IO
PWR
3.3V-1.25V Power supply for outputs.
53
SRCC8 / CPUC2_ITP
O, DIF Selectable complementary differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
54
SRCT8 / CPUT2_ITP,
O, DIF Selectable True differential CPU or SRC clock output.
ITP_EN = 0 @ CK_PWRGD assertion = SRC8
ITP_EN = 1 @ CK_PWRGD assertion = CPU2
55
NC
No connect.
56
VDD_CPU_IO
PWR
3.3V-1.25V Power supply for outputs.
57
CPUC1
O, DIF Complementary differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
58
CPUT1
O, DIF True differential CPU clock outputs.
Note that CPU1 is the iAMT clock and is on in that mode.
59
VSS_CPU
GND
Ground for outputs.
60
CPUC0
O, DIF Complement differential CPU clock outputs.
61
CPUT0
O, DIF True differential CPU clock outputs.
62
VDD_CPU
PWR
3.3V Power supply for CPU PLL.
63
CKPWRGD / PWRDWN#
I
3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A,
FS_B, FS_C, GLCK_SEL and ITP_EN.
After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for
asserting power down (active LOW).
64
FSB / TEST_MODE
I
3.3V-tolerant input for CPU frequency selection / Selects Ref/N or Tri-state
when in test mode.
0 = Tri-state, 1 = Ref/N
Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.
QFN Pin Definitions (continued)
Pin No.
Name
Type
Description
TSSOP Pin Definitions
Pin No.
Name
Type
Description
1
PCI0 / CR#_A
I/O, SE 33 MHz clock/3.3V Clock Request # Input.
Selected via CR#_A_EN bit located in byte 5 bit 7.
The CR#_A_SEL bit in byte 5 bit 6 will select to control SRC0 or SRC2 when
asserted.
2
VDD_PCI
PWR
3.3V Power supply for PCI PLL.
3
PCI1 / CR#_B
I/O, SE 33 MHz Clock/3.3V Clock Request # Input.Selected via CR#_B_EN bit located
in byte 5 bit 5.
The CR#_B_SEL bit in byte 5 bit 4 will select to control SRC1 or SRC4 when
asserted.
4
PCI2 / TME
I/O, SE 33 MHz clock output / 3.3V-tolerance input for enabling trusted mode
Sampled at CKPWRGD assertion:
0 = Normal mode, 1 = Trusted mode (no overclocking)
5
PCI3
O, SE 33 MHz clock output
相關(guān)PDF資料
PDF描述
SL28610BLC 100 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC48
SL28647CLCT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC72
SL28779CLCT 133 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC32
SL28PCIE26ALIT OTHER CLOCK GENERATOR, QCC32
SL28PCIE26ALI OTHER CLOCK GENERATOR, QCC32
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SL28610BLC 功能描述:時鐘發(fā)生器及支持產(chǎn)品 AtomPoulsbo Handheld Embed.1.5V PCIe G1 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SL28610BLCT 功能描述:時鐘發(fā)生器及支持產(chǎn)品 AtomPoulsbo Handheld Embed.1.5V PCIe G1 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SL28610BLI 功能描述:時鐘發(fā)生器及支持產(chǎn)品 AtomPoulsbo Handheld Embed.1.5V PCIe G1 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SL28610BLIT 功能描述:時鐘發(fā)生器及支持產(chǎn)品 AtomPoulsbo Handheld Embed.1.5V PCIe G1 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SL28610BLITR 制造商:Silicon Laboratories Inc 功能描述: