參數(shù)資料
型號(hào)： SL28505ALC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： PROC SPECIFIC CLOCK GENERATOR, QCC64
封裝： 9 X 9 MM, 0.50 MM PITCH, ROHS COMPLIANT, QFN-64
文件頁(yè)數(shù)： 8/28頁(yè)
文件大小： 312K
代理商： SL28505ALC
SL28505
Rev 1.0 April 24, 2008
Page 16 of 28
PD# Deassertion
The power-up latency is less than 1.8 ms. This is the time from
the deassertion of the PD# pin or the ramping of the power
supply until the time that stable clocks are output from the
clock chip. All differential outputs stopped in a three-state
condition resulting from power down will be driven high in less
than 300
s of PD# deassertion to a voltage greater than
200 mV. After the clock chip’s internal PLL is powered up and
locked, all outputs will be enabled within a few clock cycles of
each other. Below is an example showing the relationship of
clocks coming up.
CPU_STP# Assertion
The CPU_STP# signal is an active LOW input used to
synchronously stop and start the CPU output clocks while the
rest of the clock generator continues to function. When the
CPU_STP# pin is asserted, all CPU outputs that are set with
the SMBus configuration to be stoppable via assertion of
CPU_STP# are stopped within two to six CPU clock periods
after being sampled by two rising edges of the internal CPUC
clock. The final states of the stopped CPU signals are CPUT
= HIGH and CPUC = LOW.
CPU_STP# Deassertion
The deassertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner, synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles.
DOT96C
PD#
CPUC, 133MHz
CPUT, 133MHz
SRCC 100MHz
USB, 48MHz
DOT96T
SRCT 100MHz
Tstable
<1.8ms
PCI, 33MHz
REF
Tdrive_PW RDN#
<300
S, >200mV
Figure 4. PD Deassertion Timing Waveform
CP U_ S T P #
CP UT
CP UC
Figure 5. CPU_STP# Assertion Waveform
CPU _ ST P#
CPU T
CP UC
C P U T In te rn a l
T d r ive_ C P U _ S T P #,10 ns > 2 0 0 m V
C P U C In te rn a l
Figure 6. CPU_STP# Deassertion Waveform
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SL28506BZC 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SL28506BZC-2 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SL28506BZC-2T 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SL28506BZCT 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SL28506BZI 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CK505 v1.1 PCIe Gen2 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
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