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參數(shù)資料
| 型號： | SKY72310-362LF |
| 廠商： | Skyworks Solutions Inc |
| 文件頁數(shù)： | 3/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTHESIZER 2.1GHZ 24-QFN |
| 產(chǎn)品目錄繪圖： | 24-QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 分?jǐn)?shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘，晶體 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.1GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁面： | 587 (CN2011-ZH PDF) |
| 其它名稱： | 863-1080-6 |
DATA SHEET SKY72310 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
200705E Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 30, 2008
11
Table 3. Multiplexer Output
Multiplexer Output Select
(Bit 8)
Multiplexer Output Select
(Bit 7)
Multiplexer Output Select
(Bit 6)
Multiplexer Output
(Mux_out, Pin 24)
0
Reference Oscillator
0
1
Unused
0
1
0
Reference Frequency (Fref_main)
0
1
Unused
1
0
Phase Detector Frequency (Fpd_main)
1
0
1
Serial data out
1
0
Serial interface test output
1
Unused
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
1
0
00
0
X
Reserved Bits
Modulation Data Magnitude Offset
Modulation Data Input Select
Modulation Address Disable
C1425
Figure 11. Modulation Control Register (Write Only)
Synthesizer Mode = One-bit flag to power down the Σ
modulator and fractional unit. When this bit is cleared, the
synthesizer is in fractional-N mode. When this bit is set, the
synthesizer is in integer-N mode.
Synthesizer Σ Fractionality = One-bit flag to configure the size
of the
Σ modulator. This has a direct effect on power
consumption, and on the level of fractionality and step size.
When this bit is cleared, the
Σ modulator is 18-bit with a
fractionality of 218 and a step size of Fref_main/262144. When this
bit is set, the
Σ modulator is 10-bit with a fractionality of 210
and a step size of Fref_main/1024.
NOTE: There are no special power-up sequences required for the
SKY72310.
Multiplexer Output Selection = Three-bit value that selects
which internal signal is output to the Mux_out pin. The following
internal signals are available on this pin:
Reference oscillator: F
ref
Divided reference (post-reference frequency divider): F
ref_main
Phase detector frequency (post-frequency divider): F
pd_main
Serial data out for loop-back and test purposes
Refer to Table 3 for more information.
Mux_out Pin Tri-State Enable = One-bit flag to tri-state the
Mux_out pin. When this bit is cleared, the Mux_out pin is
enabled. When this bit is set, the Mux_out pin is tri-stated.
The Modulation Control Register is used to configure the
modulation unit of the main synthesizer. The modulation unit adds
or subtracts a frequency offset to the selected center frequency at
which the main synthesizer operates. The size of the modulation
data sample, controlled by the duration of the CS signal, can be
from 2 to 12 bits wide to provide from 4 to 4096 selectable
frequency offset steps.
The modulation data magnitude offset selects the magnitude
multiplier for the modulation data and can be from 0 to 8. As
shown in Figure 11, the values to be loaded are:
Modulation Data Magnitude Offset = Four-bit value that
indicates the magnitude multiplier (m) for the modulation data
samples. Valid values range from 0 to 13, effectively providing a
2m multiplication of the modulation data sample.
Modulation Data Input Select = One-bit flag to indicate the pin
on which modulation data samples are serially input when the
CS signal is between 2 and 12 bits long. When this bit is
cleared, modulation data samples are to be presented on the
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