參數(shù)資料
型號: SKY72310-362LF
廠商: Skyworks Solutions Inc
文件頁數(shù): 15/19頁
文件大小: 0K
描述: IC SYNTHESIZER 2.1GHZ 24-QFN
產(chǎn)品目錄繪圖: 24-QFN
標準包裝: 1
類型: 分數(shù) N 合成器(RF)
PLL:
輸入: 時鐘,晶體
輸出: 時鐘,晶體
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.1GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN 裸露焊盤(4x4)
包裝: 標準包裝
產(chǎn)品目錄頁面: 587 (CN2011-ZH PDF)
其它名稱: 863-1080-6
DATA SHEET SKY72310 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
200705E Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 30, 2008
5
Case 1: To achieve a desired Fvco_main frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation
of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal
frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz. Therefore:
Nfractional
=
Fvco_main
Fdiv_ref
= 902.4530
20
= 45.12265
The value to be programmed in the Divider Register is:
Nreg
= Round[Nfractional] – 32
= Round[45.12265] – 32
= 45 – 32
= 13 (decimal)
= 000001101 (binary)
With the modulator in 18-bit mode, the value to be programmed in the Dividend Registers is:
dividend = Round[divider × (Nfractional – Nreg – 32)]
= Round[262144 × (45.12265 – 13 – 32)]
= Round[262144 × (0.12265)]
= Round[32151.9616]
= 32152 (decimal)
= 000111110110011000 (binary)
where 00 0111 1101 is loaded in the Dividend MSB Register and 1001 1000 is loaded in the Dividend LSB Register.
Summary:
Divider Register = 0 0000 1101
Dividend LSB Register = 1001 1000
Dividend MSB Register = 00 0111 1101
The resulting VCO frequency is 902.453 MHz
Step size is 76.3 Hz
Note: The frequency step size for this case is 20 MHz divided by 218, giving 76.3 Hz.
S1059
Figure 4. Fractional-N Applications: Sample Calculation (1 of 2)
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