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參數(shù)資料
| 型號： | SKY72310-362LF |
| 廠商： | Skyworks Solutions Inc |
| 文件頁數(shù)： | 17/19頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER 2.1GHZ 24-QFN |
| 產(chǎn)品目錄繪圖： | 24-QFN |
| 標準包裝： | 1 |
| 類型： | 分數(shù) N 合成器（RF） |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘，晶體 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.1GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN 裸露焊盤（4x4） |
| 包裝： | 標準包裝 |
| 產(chǎn)品目錄頁面： | 587 (CN2011-ZH PDF) |
| 其它名稱： | 863-1080-6 |
DATA SHEET SKY72310 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
200705E Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 30, 2008
7
Integer-N Applications. The desired division ratio for the
synthesizer is given by:
ref
_
div
main
_
vco
eger
int
F
N
=
where Ninteger is an integer number from 32 to 543.
The value to be programmed in the Divider Register is given by:
32
N
eger
int
reg
=
When in integer mode, allowed values for Nreg are from 0 to 511.
NOTE: As with all integer-N synthesizers, the minimum step size
is related to the crystal frequency and reference frequency
division ratio.
Register Loading Order. In applications where the synthesizer is
in 18-bit mode, the Dividend MSB Register holds the 10 MSBs of
the dividend and the Dividend LSB Register holds the 8 LSBs of
the dividend. The registers that control the synthesizer’s divide
ratio are to be loaded in the following order:
Divider Register
Dividend LSB Register
Dividend MSB Register (at which point the new divide ratio
takes effect)
In applications where the synthesizer is in 10-bit mode, the
Dividend MSB Register holds the 10 bits of the dividend. The
registers that control the synthesizer’s divide ratio are to be
loaded in the following order:
Divider Register
Dividend MSB Register (at which point the new divide ratio
takes effect)
NOTE: When in integer mode, the new divide ratios take effect as
soon as the Divider Register is loaded.
Direct Digital Modulation
The high fractionality and small step size of the SKY72310 allow
the user to tune to practically any frequency in the VCO’s
operating range. This allows direct digital modulation by
programming the different desired frequencies at precise instants.
Typically, the channel frequency is programmed by the Main
Divider and MSB/LSB Dividend Registers, and the instantaneous
frequency offset from the carrier is programmed by the
Modulation Data Register.
The Modulation Data Register can be accessed in three ways as
defined in the following subsections.
Normal Register Write. A normal 16-bit serial interface write
occurs when the CS signal is 16 clock cycles wide. The
corresponding 16-bit modulation data is simultaneously
presented to the Data pin. The content of the Modulation Data
Register is passed to the modulation unit at the next falling edge
of the divided main VCO frequency (Fpd_main).
Short CS Through Data Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented to the Data pin. The Data
pin is the default pin used to enter modulation data directly in the
Modulation Data Register with shortened CS strobes.
This method of data entry eliminates the register address
overhead on the serial interface. All serial interface bits are re-
synchronized internally at the reference oscillator frequency. The
content of the Modulation Data Register is passed to the
modulation unit at the next falling edge of the divided main VCO
frequency (Fpd_main).
Short CS Through Mod_in Pin (No Address Bits Required). A
shortened serial interface write occurs when the CS signal is from
2 to 12 clock cycles wide. The corresponding modulation data (2
to 12 bits) is simultaneously presented on the Mod_in pin, an
alternate pin used to enter modulation data directly into the
Modulation Data Register with shortened CS strobes. This mode is
selected through the Modulation Control Register.
This method of data entry also eliminates the register address
overhead on the serial interface and allows a different device than
the one controlling the channel selection to enter the modulation
data (e.g., a microcontroller for channel selection and a digital
signal processor for modulation data).
All serial interface bits are internally re-synchronized at the
reference oscillator frequency and the content of the Modulation
Data Register is passed to the modulation unit at the next falling
edge of the divided main VCO frequency (Fpd_main).
Modulation data samples in the Modulation Data Register can be
from 2 to 12 bits long, and enable the user to select how many
distinct frequency steps are to be used for the desired modulation
scheme.
The user can also control the frequency deviation through the
modulation data magnitude offset in the Modulation Control
Register. This allows shifting of the modulation data to
accomplish a 2m multiplication of frequency deviation.
NOTE: The programmable range of –0.5 to +0.5 of the main
Σ modulator can be exceeded up to the condition where
the sum of the dividend and the modulation data conform
to:
5625
.
0
)
dividend
N
(
5625
.
0
mod
+
≤
+
≤
When the sum of the dividend and modulation data lie outside this
range, the value of Ninteger must be changed.
For a more detailed description of direct digital modulation
functionality, refer to the Skyworks Application Note, Direct Digital
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