參數(shù)資料
型號(hào): SKY72300-362
廠商: Skyworks Solutions Inc
文件頁(yè)數(shù): 5/20頁(yè)
文件大?。?/td> 0K
描述: IC SYNTHESIZER 2.1GHZ 24QFN
產(chǎn)品目錄繪圖: 24-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 分?jǐn)?shù) N 合成器
PLL:
輸入: 時(shí)鐘,晶體
輸出: 時(shí)鐘,晶體
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.1GHz
除法器/乘法器: 是/無(wú)
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 587 (CN2011-ZH PDF)
其它名稱: 863-1077-6
DATA SHEET SKY72300-362 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
200731B Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 30, 2007
13
A3
A2
A1
A0
11
10
9
8
7
6
5
4
3
2
1
0
1
X
MSB
LSB
Full Power Down
Main Synthesizer Power Down
Main Synthesizer Mode
Main Synthesizer
ΔΣ Fractionality
Auxiliary Synthesizer Power Down
Auxiliary Synthesizer Mode
Multiplexer Output Selection
Mux_out Pin Tri-State Enable
C1424
Figure 13. Power Down and Multiplexer Output Register (Write Only)
Table 4. Multiplexer Output
Multiplexer Output Select
(Bit 8)
Multiplexer Output Select
(Bit 7)
Multiplexer Output Select
(Bit 6)
Multiplexer Output
(Mux_out)
0
Reference Oscillator
0
1
Auxiliary Reference Frequency (Fref_aux)
0
1
0
Main Reference Frequency (Fref_main)
0
1
Auxiliary Phase Detector Frequency (Fpd_aux)
1
0
Main Phase Detector Frequency (Fpd_main)
1
0
1
Serial data out
1
0
Serial interface test output
1
Unused
Main Synthesizer Σ Fractionality = One-bit flag to configure
the size of the main
Σ modulator. This has a direct effect on
power consumption, and on the level of fractionality and step
size. When this bit is cleared, the main
Σ modulator is 18-bit
with a fractionality of 218 and a step size of Fref_main/262144.
When this bit is set, the main
Σ modulator is 10-bit with a
fractionality of 210 and a step size of Fref_main/1024.
Auxiliary Synthesizer Power Down = One-bit flag to power down
the auxiliary synthesizer. When this bit is cleared, the auxiliary
synthesizer is powered up. When this bit is set, the auxiliary
synthesizer is in power-down mode.
Auxiliary Synthesizer Mode = One-bit flag to power down the
auxiliary synthesizer’s
Σ modulator and fractional unit to
operate as an integer-N synthesizer. When this bit is cleared,
the auxiliary synthesizer is in fractional-N mode. When this bit is
set, the auxiliary synthesizer is in integer-N mode.
NOTE: There are no special power-up sequences required for the
SKY72300-362.
Multiplexer Output Selection = Three-bit value that selects
which internal signal is output to the Mux_out pin. The following
internal signals are available on this pin:
Reference oscillator: F
ref
Main or auxiliary divided reference (post-reference frequency
main or auxiliary dividers): Fref_main or Fref_aux
Main or auxiliary phase detector frequency (post-main or
auxiliary frequency dividers): Fpd_main or Fpd_aux
Serial data out for loop-back and test purposes
Refer to Table 4 for more information.
Mux_out Pin Tri-State Enable = One-bit flag to tri-state the
Mux_out pin. When this bit is cleared, the Mux_out pin is
enabled. When this bit is set, the Mux_out pin is tri-stated.
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