參數(shù)資料
型號(hào): SKY72300-362
廠商: Skyworks Solutions Inc
文件頁數(shù): 20/20頁
文件大?。?/td> 0K
描述: IC SYNTHESIZER 2.1GHZ 24QFN
產(chǎn)品目錄繪圖: 24-QFN
標(biāo)準(zhǔn)包裝: 1
類型: 分?jǐn)?shù) N 合成器
PLL:
輸入: 時(shí)鐘,晶體
輸出: 時(shí)鐘,晶體
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 2.1GHz
除法器/乘法器: 是/無
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 24-QFN(4x4)
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁面: 587 (CN2011-ZH PDF)
其它名稱: 863-1077-6
DATA SHEET SKY72300-362 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
200731B Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice July 30, 2007
9
Table 1. SKY72300-362 Register Map
Address (Hex)
Register (Note 1)
Length (Bits)
Address (Bits)
0
Main Divider Register
12
4
1
Main Dividend MSB Register
12
4
2
Main Dividend LSB Register
12
4
3
Auxiliary Divider Register
12
4
Auxiliary Dividend Register
12
4
5
Reference Frequency Dividers Register
12
4
6
Phase Detector/Charge Pump Control Register
12
4
7
Power Down/Multiplexer Output Select Control Register
12
4
8
Modulation Control Register
12
4
9
Modulation Data Register
Modulation Data Register (Note 2) — direct input
12
2 ≤ length ≤ 12 bits
4
0
Note 1: All registers are write only.
Note 2: No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.
This method of data entry also eliminates the register address
overhead on the serial interface and allows a different device than
the one controlling the channel selection to enter the modulation
data (e.g., a microcontroller for channel selection and a digital
signal processor for modulation data).
All serial interface bits are internally re-synchronized at the
reference oscillator frequency and the content of the Modulation
Data Register is passed to the modulation unit at the next falling
edge of the divided main VCO frequency (Fpd_main).
Modulation data samples in the Modulation Data Register can be
from 2 to 12 bits long, and enable the user to select how many
distinct frequency steps are to be used for the desired modulation
scheme.
The user can also control the frequency deviation through the
modulation data magnitude offset in the Modulation Control
Register. This allows shifting of the modulation data to
accomplish a 2m multiplication of frequency deviation.
NOTE: The programmable range of –0.5 to +0.5 of the main
Σ modulator can be exceeded up to the condition where
the sum of the dividend and the modulation data conform
to:
5625
.
0
)
dividend
N
(
5625
.
0
mod
+
+
When the sum of the dividend and modulation data lie outside this
range, the value of Ninteger must be changed.
For a more detailed description of direct digital modulation
functionality, refer to the Skyworks Application Note, Direct Digital
Modulation Using the SKY72300, SKY72301, and SKY72302 Dual
Synthesizers/PLLs (document number 101349).
Register Descriptions
Table 1 lists the 10 16-bit registers that are used to program the
SKY72300-362. All register writes are programmed address first,
followed directly with data. MSBs are entered first. On power up,
all registers are reset to 0x000 except registers at addresses 0x0
and 0x3, which are set to 0x006.
Main Synthesizer Registers
The Main Divider Register contains the integer portion closest to
the desired fractional-N (or the integer-N) value minus 32 for the
main synthesizer. This register, in conjunction with the Main
Dividend MSB and LSB Registers (which control the fraction offset
from –0.5 to +0.5), allows selection of a precise frequency. As
shown in Figure 6, the value to be loaded is:
Main Synthesizer Divider Index = Nine-bit value for the integer
portion of the main synthesizer dividers. Valid values for this
register are from 6 to 505 (fractional-N) or 0 to 511 (integer-N).
The Main Dividend MSB and LSB Registers control the fraction
part of the desired fractional-N value and allow an offset of –0.5
to +0.5 to the main integer selected through the Main Divider
Register. As shown in Figures 7 and 8, values to be loaded are:
Main Synthesizer Dividend (MSBs) = Ten-bit value for the MSBs
of the 18-bit dividend for the main synthesizer.
Main Synthesizer Dividend (LSBs) = Eight-bit value for the LSBs
of the 18-bit dividend for the main synthesizer.
The Main Dividend Register MSB and LSB values are 2's
complement format.
NOTE: When in 10-bit mode, the Main Dividend LSB Register is
not required.
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