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參數(shù)資料
| 型號： | SKY72300-362 |
| 廠商： | Skyworks Solutions Inc |
| 文件頁數(shù)： | 15/20頁 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER 2.1GHZ 24QFN |
| 產品目錄繪圖： | 24-QFN |
| 標準包裝： | 1 |
| 類型： | 分數(shù) N 合成器 |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | 時鐘，晶體 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 2.1GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 3.3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤 |
| 供應商設備封裝： | 24-QFN（4x4） |
| 包裝： | 標準包裝 |
| 產品目錄頁面： | 587 (CN2011-ZH PDF) |
| 其它名稱： | 863-1077-6 |
DATA SHEET SKY72300-362 FREQUENCY SYNTHESIZER
Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 sales@skyworksinc.com www.skyworksinc.com
4
July 30, 2007 Skyworks Proprietary and Confidential information Products and Product Information are Subject to Change Without Notice 200731B
Reference Frequency Dividers
The crystal oscillator signal can be divided by a ratio of 1 to 32 to
create the reference frequencies for the phase detectors. The
SKY72300-362 has both a main and an auxiliary frequency
synthesizer, and provides independently configurable dividers of
the crystal oscillator frequency for both the main and auxiliary
phase detectors. The divide ratios are programmed by the
Reference Frequency Dividers Register.
NOTE: The divided crystal oscillator frequencies (which are the
internal reference frequencies), Fref_main and Fref_aux,
are referred to as reference frequencies throughout this
document.
Phase Detectors and Charge Pumps
The SKY72300-362 uses a separate charge pump phase detector
for each synthesizer which provides a programmable gain, Kd,
from 31.25 to 1000
A/2π radians in 32 steps programmed using
the Phase Detector/Charge Pump Control Register.
Frequency Steering
When programmed for frequency power steering, the SKY72300-
362 has a circuit that helps the loop filter steer the VCO, through
the LD/PSmain signal (pin 4). In this configuration, the LD/PSmain
signal can provide for more rapid acquisition.
When programmed for lock detection, internal frequency steering
is implemented and provides frequency acquisition times
comparable to conventional phase/frequency detectors.
Lock Detection
When programmed for lock detection, the SKY72300-362
provides an active low, pulsing open collector output using the
LD/PSmain signal (pin 4) to indicate the out-of-lock condition.
When locked, the LD/PSmain signal is tri-stated (high
impedance).
Power Down
The SKY72300-362 supports a number of power-down modes
through the serial interface. For more information, see the
Register Descriptions section of this document.
Serial Interface Operation
The serial interface consists of three pins: Clock (pin 22), Data
(pin 20), and CS (pin 21). The Clock signal controls data on the
two serial data lines (Data and CS). The Data pin bits shift into a
temporary register on the rising edge of Clock. The CS line allows
individual selection transfers that synchronize and sample the
information of slave devices on the same bus.
Figure 3 depicts how a serial transfer takes place functionally.
A serial transfer is initiated when a microcontroller or
microprocessor forces the CS line to a low state. This is followed
immediately by an address/data stream sent to the Data pin that
coincides with the rising edges of the clock presented on the
Clock line.
Each rising edge of the Clock signal shifts in one bit of data on the
Data line into a shift register. At the same time, one bit of data is
shifted out of the Mux_out pin (if the serial bit stream is selected)
at each falling edge of Clock. To load any of the registers, 16 bits
of address or data must be presented to the Data line with the
LSB last while the CS signal is low. If the CS signal is low for
more than 16 clock cycles, only the last address or data bits are
used to load the registers.
If the CS signal is brought to a high state before the 13th Clock
edge, the bit stream is assumed to be modulation data samples.
In this case, it is assumed that no address bits are present and
that all the bits in the stream should be loaded into the
Modulation Data Register.
Register Programming
Register programming equations, described in this section, use
the following variables and constants:
Nfractional
Desired VCO division ratio in fractional-N applications.
This is a real number and can be interpreted as the
reference frequency (Fref) multiplying factor such that
the resulting frequency is equal to the desired VCO
frequency.
Ninteger
Desired VCO division ratio in integer-N applications.
This number is an integer and can be interpreted as
the reference frequency (Fref) multiplying factor so that
the resulting frequency is equal to the desired VCO
frequency.
Nreg
Nine-bit unsigned input value to the divider ranging
from 0 to 511 (integer-N mode) and from 6 to 505
(fractional-N mode).
divider
This constant equals 262144 when the
Σ modulator
is in 18-bit mode, and 1024 when the
Σ modulator is
in 10-bit mode.
dividend When in 18-bit mode, this is the 18-bit signed input
value to the
Σ modulator, ranging from
–131072 to +131071 and providing 262144 steps,
each step equal to Fdiv_ref/218 Hz.
When in 10-bit mode, this is the 10-bit signed input
value to the
Σ modulator, ranging from
–512 to +511 and providing 1024 steps, each step
equal to Fdiv_ref/210 Hz.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SKY72301-22 | 功能描述:鎖相環(huán) - PLL 1GHz / 500MHz Syn. Phase noise-96dBc/Hz RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| SKY72302 | 制造商:SKYWORKS 制造商全稱:SKYWORKS 功能描述:Spur-Free, 6.1 GHz Dual Fractional-N Frequency Synthesizer |
| SKY72302-21 | 功能描述:時鐘合成器/抖動清除器 6.1GHz 400Hz step Freq. Synthesizer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SKY72310-362 | 功能描述:IC SYNTHESIZER 2.1GHZ 24QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 產品變化通告:Product Discontinuation 04/May/2011 標準包裝:96 系列:- 類型:時鐘倍頻器，零延遲緩沖器 PLL:帶旁路 輸入:LVTTL 輸出:LVTTL 電路數(shù):1 比率 - 輸入:輸出:1:8 差分 - 輸入:輸出:無/無 頻率 - 最大:133.3MHz 除法器/乘法器:是/無 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:管件 其它名稱:23S08-5HPGG |
| SKY72310-362LF | 功能描述:IC SYNTHESIZER 2.1GHZ 24-QFN RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標準包裝:2,000 系列:- 類型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無/無 頻率 - 最大:1GHz 除法器/乘法器:是/無 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應商設備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱:NJW1504V-TE1-NDNJW1504V-TE1TR |
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