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參數(shù)資料
| 型號： | SK100EL131PJ |
| 元件分類： | 鎖存器 |
| 英文描述： | 100E SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PQCC28 |
| 封裝： | PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 86K |
| 代理商： | SK100EL131PJ |
HIGH-PERFORMANCE PRODUCTS
1
www.semtech.com
Revision 1/August 22, 2001
SK10/100E131
4-Bit D Flip-Flop
Description
Features
Functional Block Diagram
The SK10E/100E131 is a Quad master-slave D-type flip-
flop with differential outputs.
Each flip-flop may be
clocked separately by holding Common Clock (CC) LOW
and using the Clock Enable (CE*) inputs for clocking.
Common clocking is achieved by holding the CE inputs
LOW and using CC to clock all four flip-flops. In this
case, the CE* inputs perform the function of controlling
the common clock to each flip-flop.
Individual asynchronous resets are provided (R).
Asynchronous set controls (S) are ganged together in
pairs, with the pairing chosen to reflect physical chip
symmetry.
Data enters the master when both CC and CE* are LOW,
and transfers to the slave when either CC or CE (or both)
go HIGH.
1100 MHz Minimum Toggle Frequency
Differential Outputs
Individual and Common Clocks
Individual Resets (asynchronous)
Paired Sets (asynchronous)
Extended 100E VEE Range of –4.2V to –5.5V
Internal 75K
W Input Pulldown Resistors
Fully Compatible with MC10/100E131
Specified Over Industrial Temperature Range:
–40oC to +85oC
ESD Protection of >4000V
Available in 28-pin PLCC Package
Q3
Q3*
S
D
Q
R
D3
CE3*
R3
S
D
Q
R
Q0
Q0*
D0
R0
CEO*
S
D
Q
R
Q1
Q1*
S
D
Q
R
Q2
Q2*
D2
CE2*
R2
D1
CE1
R1
CC
S12
S03
PIN Description
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0
D-
3
D
*
0
E
C-
*
3
E
C
0
R-
3
R
C
2
1
S
,
3
0
S
0
Q-
3
Q
*
0
Q-
*
3
Q
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Pin Names
Pinout
Q2*
Q2
VCC
Q1*
Q1
Q0*
Q0
CE3*
D3
S12
VEE
CC
S03
D0
CE0*
R0
D1
CE1*
R1
NC
VC
C0
R3
D2
CE2*
R2
VC
C0
Q3*
Q3
1
2
3
4
25
24
23
22
21
20
19
56
7
8
9
10
11
26
27
28
18
17
16
15
14
13
12
28 Lead PLCC
(Top View)
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