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參數(shù)資料
| 型號： | SK100EL34WD |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大小： | 83K |
| 代理商： | SK100EL34WD |
HIGH-PERFORMANCE PRODUCTS
1
www.semtech.com
Revision 3/June 26, 2002
SK100EL34W
÷2, ÷4, ÷8 Clock Generation Chip
Description
.eatures
.unctional Block Diagram
The SK100EL34W are low skew, ÷2, ÷4, ÷8 clock
generation chips designed explicitly for low skew clock
generation applications.
The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned.
This device is
functionally compatible with On-Semiconductor’s
MC100EL34. These devices can be driven by either a
differential or single-ended ECL or, if positive power
supplies are used, PECL input signal. In addition, by
using the VBB output, a sinusoidal source can be AC-
coupled into the device. The EL34W provides a VBB
output for single-ended use or DC bias for AC coupling
to the device.
VBB is an output pin and should be
used as a bias for the EL34W as its current source/
sink capability is limited up to 0.5 mA.
Whenever
used, the VBB output should be bypassed to VCC via a
0.01 F capacitor.
The common enable (EN*) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids any
chance of generating a runt clock pulse on the internal
clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal
divider stages. The internal enable flip-flop is clocked
on the falling edge of the input clock, therefore, all
associated specification limits are referenced to the
negative edge of the clock input.
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple EL34Ws in a system.
Extended Supply Voltage Range: (VEE = –3.0V to
–5.5V, VCC = 0V) or (VCC = +3.0V to +5.5V,
VEE = 0V)
50 ps Output-to-Output Skew
VBB Output
Synchronous Enable/Disable
Master Reset for Synchronization
Internal 75K
Input Pull-Down Resistors
Fully Compatible with MC100EL34
Specified Over Industrial Temperature Range:
–40oC to 85oC
ESD Protection of >4000V
Available in 16-Pin SOIC Package
Q0
Q0*
Q1*
VCC
Q2
Q2*
VCC
Q1
VCC
EN*
CLK*
VBB
MR
VEE
NC
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
÷ 2
R
Q
R
Q
D
÷ 8
R
Q
÷ 4
R
Q
相關PDF資料 |
PDF描述 |
|---|---|
| SK100EL39WDT | 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| SK100EL52WU | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC |
| SK100EL52WDT | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO8 |
| SK100EL56WDT | 100EL SERIES, DUAL 2 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, PDSO20 |
| SK100EL57WU | 100E SERIES, 4 LINE TO 1 LINE MULTIPLEXER, COMPLEMENTARY OUTPUT, UUC |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SK100ELT21W | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WD | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WDT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WU | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100EP111 | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Low-Voltage 1:10 Differential ECL/PECL/HSTL Clock Driver |
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