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參數(shù)資料
| 型號(hào)： | SK100EL31WU |
| 元件分類： | 鎖存器 |
| 英文描述： | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC |
| 封裝： | DIE |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 375K |
| 代理商： | SK100EL31WU |
TEST AND MEASUREMENT PRODUCTS
1
www.semtech.com
Revision 3 / January 24, 2003
SK100EL31W
D Flip - Flop with Set and Reset
Description
Features
Functional Block Diagram
The SK100EL31W is a D Flip-Flop with Set and Reset. The
device is fully compatible with the MC100EL31 and
MC100LVEL31 devices, but operates from a 5.5V to
3.3V supply. With propagation delays and output transition
times significantly faster than the E131, SK100EL31W is
ideally suited for those applications which require the
ultimate in AC performance. Both set and reset inputs are
asynchronous, level triggered signals. Data enters the
master portion of the flip-flop when clock is LOW, is
transferred to the slave and thus the outputs, upon a
positive transition of the clock.
Extended Supply Voltage Range: (VEE = 5.5V to
3.0V, VCC = 0V) or (VCC = +3.0V to +5.5V, VEE = 0V)
350 ps typical Propagation Delay
2.9 GHz Toggle Frequency
Fully Compatible with MC100EL31
and MC100LVEL31
75K Internal Input Pulldown Resistors
Specified Over Industrial Temperature Range:
40oC to 85oC
ESD Protection of >4000V
Small Outline SOIC Package
Flammability Rate: UL-94 code V-0.
Moisture Sensitivity: Level 1.
1
2
3
4
8
7
6
5
S
R
D
CLK
VCC
VEE
Q
Q*
Flip Flop
D
S
R
PinDescription
n
i
Pn
o
it
c
n
u
F
*
Q
,
Q
S
D
K
L
C
R
s
t
u
p
t
u
O
a
t
a
D
t
e
S
t
u
p
n
I
a
t
a
D
t
u
p
n
I
k
c
o
l
C
t
e
s
e
R
DS
R
K
L
CQ
L
H
X
L
H
L
H
L
H
Z
X
L
H
L
f
e
d
n
U
Truth Table
Z = LOW to HIGH Transition
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SK100EL32WD | 100EL SERIES, PRESCALER, PDSO8 |
| SK100EL33WD | 100EL SERIES, PRESCALER, PDSO8 |
| SK100EL34WD | 100EL SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| SK100EL39WDT | 100E SERIES, LOW SKEW CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| SK100EL52WU | 100EL SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, UUC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SK100EL34WD | 制造商:Semtech Corporation 功能描述:Clock Divider 16-Pin SOIC |
| SK100ELT21W | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WD | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WDT | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
| SK100ELT21WU | 制造商:SEMTECH 制造商全稱:Semtech Corporation 功能描述:Differential PECL to CMOS/TTL or LVPECL to LVCMOS/LVTTL Translator |
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