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參數(shù)資料
| 型號(hào)： | SI5364 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION PORT CARD CLOCK IC |
| 中文描述： | SONET / SDH的精密端口卡時(shí)鐘IC |
| 文件頁數(shù)： | 29/40頁 |
| 文件大?。?/td> | 565K |
| 代理商： | SI5364 |
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Si5364
Rev. 2.2
29
B1
AUTOSEL
I*
LVTTL
Automatic Switching Mode Select.
When 1, the clock input used by the DSPLL to gener-
ate the SONET/SDH clock outputs is selected auto-
matically. The automatic switching mode initially
selects the highest priority clock available, with the
priorities indicated below:
CLKIN_A: Highest Priority
CLKIN_B: Second Highest Priority
REF/CLKIN_F: Lowest Priority
If the selected input clock fails because of an LOS or
FOS alarm condition, the next lower priority clock
that is available is selected.
If an input clock that has a higher priority than the
currently-selected clock becomes available, the
higher priority clock is selected only if RVRT is
active. If RVRT is not active, automatic switching to a
higher priority clock is disabled.
A7
A_ACTV
O
LVTTL
CLKIN_A is Active.
Active high output indicates that CLKIN_A is
selected as the clock input to the DSPLL.
The DH_ACTV output takes precedence over this
signal as an indicator of the DSPLL clock input sta-
tus. When this output is high and the DH_ACTV out-
put is low, CLKIN_A is being used by the DSPLL to
generate the SONET/SDH compatible output clocks.
When this output is high and the DH_ACTV output is
high, CLKIN_A is selected, but the DSPLL is in digi-
tal hold mode. See DH_ACTV.
A8
B_ACTV
O
LVTTL
CLKIN_B is Active.
Active high output indicates that CLKIN_B is
selected as the clock input to the DSPLL.
The DH_ACTV output takes precedence over this
signal as an indicator of the DSPLL clock input sta-
tus. When this output is high and the DH_ACTV out-
put is low, CLKIN_B is being used by the DSPLL to
generate the SONET/SDH compatible output clocks.
When this output is high and the DH_ACTV output is
high, CLKIN_B is selected, but the DSPLL is in
digital hold mode. See DH_ACTV.
Table 10. Pin Descriptions (Continued)
I/O
Signal Level
Pin #
Pin Name
Description
*Note:
The LVTTL inputs on the Si5364 device have an internal pulldown mechanism that causes the input to default to a logic
low state if the input is not driven from an external source.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5364BC | 制造商:SILICON 功能描述: |
| SI5364-EVB | 功能描述:時(shí)鐘和定時(shí)器開發(fā)工具 Multi/Jitter/Hitless 19 55 622MHz Out RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Modules 類型:Clock Conditioners 工具用于評(píng)估:LMK04100B 頻率:122.8 MHz 工作電源電壓:3.3 V |
| SI5364FBC | 制造商:Vishay Siliconix 功能描述: |
| SI5364-F-BC | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 Multi/Jitter/Hitless 19 55 622MHz Outpt RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| SI5364-G-BC | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precision Port Card 19 155 622 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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