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參數(shù)資料
| 型號： | SI5350B-AXXXXX-GT |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO10 |
| 封裝： | MO-137C, MSOP-10 |
| 文件頁數(shù)： | 6/22頁 |
| 文件大?。?/td> | 249K |
| 代理商： | SI5350B-AXXXXX-GT |
Si5350B
14
Rev. 0.2
4.5. Design Considerations
The Si5350B is a self-contained clock generator that requires very few external components. The following general
guidelines are recommended to ensure optimum performance.
4.5.1. Power Supply Decoupling/Filtering
The Si5350B has built-in power supply filtering circuitry to help keep the number of external components to a
minimum. All that is recommended is one 0.1 F decoupling capacitor per power supply pin. This capacitor should
be mounted as close to the VDD and VDDO pins as possible without using vias.
4.5.2. Power Supply Sequencing
The VDD and VDDOx (i.e., VDDO0, VDDO1, VDDO2, VDDO3) power supply pins have been separated to allow
flexibility in output signal levels. It is important that power is applied to all supply pins (VDD, VDDOx) at the same
time. Unused VDDOx pins should be tied to VDD.
4.5.3. External Crystal
The external crystal should be mounted as close to the pins as possible using short PCB traces. The XA and XB
traces should be kept away from other high-speed signal traces. See “AN551: Crystal Selection Guide” for more
details.
4.5.4. External Crystal Load Capacitors
The Si5350B provides the option of using internal and external crystal load capacitors. If external load capacitors
are used, they should be placed as close to the XA/XB pads as possible. See “AN551: Crystal Selection Guide” for
more details.
4.5.5. Unused Pins
Unused control pins (P0–P4) should be tied to GND.
Unused voltage control pin should be tied to GND.
Unused output pins (CLK0–CLK7) should be left floating.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| Si5350B-Axxxxx-GU | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 133MHz Clock with VCXO , 8 outputs, 24-QSOP (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-Bxxxxx-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 160 MHz Clock with VCXO , 8 outputs with 50? output impedance, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-Bxxxxx-GT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 160 MHz Clock with VCXO , 3 outputs with 50? output impedance, 10-MSOP (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5350C-A01030-GT | 制造商:Silicon Laboratories Inc 功能描述:ANY-RATE, DUAL PLL 125MHZ CLOCK WITH DUAL INPUT, 3 OUTPUTS, - Rail/Tube |
| SI5350C-A01237-GT | 制造商:Silicon Laboratories Inc 功能描述:ANY-RATE, DUAL PLL 125MHZ CLOCK WITH DUAL INPUT, 3 OUTPUTS, - Rail/Tube |
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