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參數(shù)資料
| 型號： | SI5350B-AXXXXX-GT |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 133 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO10 |
| 封裝： | MO-137C, MSOP-10 |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 249K |
| 代理商： | SI5350B-AXXXXX-GT |
Si5350B
Rev. 0.2
13
4.3.4. Power Down (PDN)
An optional power down control pin allows a full shutdown of the Si5350B to minimize power consumption when its
output clocks are not being used. The Si5350B is in normal operation when the PDN pin is held low and is in power
down mode when held high. Power consumption when the device is in power down mode is indicated in Table 3 on
4.4. Voltage Control Input (VC)
The internal VCXO generates a high-frequency clock that is controlled by the voltage control input pin (VC). The
high-frequency clock is divided down by a high-resolution fractional MultiSynth divider to generate the final output
frequency. The unique design of the VCXO eliminates the need for an external pullable crystal. A standard, low-
cost, fixed-frequency (25 MHz or 27 MHz) crystal can be used.
A unique feature of the Si5350B is its ability to generate multiple output frequencies controlled by the same control
voltage applied to the VC pin. This replaces multiple PLLs or VCXOs that would normally be locked to the same
reference. An example is illustrated in Figure 8.
Figure 8. Generating One Or More Synchronous Clocks
4.4.1. Control Voltage Gain (kV)
The voltage level on the VC pin directly controls the output frequency. The rate of change in output clock frequency
(kv) is configurable from 6 ppm/V up to 600 ppm/V. This allows a configurable pull range from ±10 ppm to
A key advantage of the VCXO design in the Si5350B is its highly linear tuning range. This allows better control of
PLL stability and jitter performance over the entire control voltage range.
Figure 9. User-definable VCXO Pull Range
CLK0
VC
Multi
Synth
2
CLK1
CLK2
Additional MultiSynths can be
added to generate multiple
synchronous clocks with
different output frequencies
XA
XB
OSC
VCXO
Multi
Synth
0
Multi
Synth
1
Control
Voltage
Fixed Frequency
Crystal (non-pullable)
f(pp
m
)
VC (Volts)
500
750
1000
-500
-750
-1000
0
250
-250
VDD
Pull-in Range
@ VDD = 3.3V
VDD
2
kv
= 6
00
pp
m/
V
kv = 6 ppm/V
10
-10
kv
= 4
50
ppm
/V
kv =
300
ppm
/V
kv = 150
ppm/V
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參數(shù)描述 |
|---|---|
| Si5350B-Axxxxx-GU | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 133MHz Clock with VCXO , 8 outputs, 24-QSOP (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-Bxxxxx-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 160 MHz Clock with VCXO , 8 outputs with 50? output impedance, 20-QFN (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| Si5350B-Bxxxxx-GT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 Any-Rate, Dual PLL 160 MHz Clock with VCXO , 3 outputs with 50? output impedance, 10-MSOP (customized) RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5350C-A01030-GT | 制造商:Silicon Laboratories Inc 功能描述:ANY-RATE, DUAL PLL 125MHZ CLOCK WITH DUAL INPUT, 3 OUTPUTS, - Rail/Tube |
| SI5350C-A01237-GT | 制造商:Silicon Laboratories Inc 功能描述:ANY-RATE, DUAL PLL 125MHZ CLOCK WITH DUAL INPUT, 3 OUTPUTS, - Rail/Tube |
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