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參數(shù)資料
| 型號： | SI5338N-A00000-GMR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁數(shù)： | 8/34頁 |
| 文件大小： | 285K |
| 代理商： | SI5338N-A00000-GMR |
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Si5338
16
Rev. 0.5
3. Functional Description
Figure 1. Si5338 Block Diagram
3.1. Overview
The Si5338 is a high performance, low jitter clock
generator capable of synthesizing four independent
user-programmable clock frequencies up to 350 MHz
and select frequencies up to 710 MHz. The device
supports free-run operation using an external crystal, or
it can lock to an external clock for generating
synchronous clocks. The output drivers support four
differential clocks, or eight single-ended clocks, or a
combination of both. The output drivers are configurable
to support common signal formats such as LVPECL,
LVDS, HCSL, CMOS, HSTL, and SSTL. Separate
output supply pins are available for generating 3.3, 2.5,
1.8, and 1.5 V signal levels. The core voltage supply
accepts 3.3, 2.5, or 1.8 V and is independent from the
output supplies.
Using its two stage synthesis architecture and patented
high-resolution MultiSynth technology, the Si5338 can
generate four independent frequencies from a single
input frequency. In addition to clock generation, the
inputs can bypass the synthesis stage enabling its use
as a high-performance clock buffer, or as a combination
of a buffer and generator.
For applications that need fine frequency adjustments
(i.e.
clock
margining),
each
of
the
synthesized
frequencies can be incremented or decremented in user
defined steps as low as 1 ppm per step. Output-to-
output phase delays are also adjustable in user defined
steps as low as 20 ps per step to compensate for PCB
trace delays or for fine tuning of set-up and hold
margins. A zero-delay buffer mode is also available to
help minimize input-to-output delay. Spread spectrum is
available on each of the clock outputs for EMI sensitive
applications such as PCI Express.
Configuration and control of the Si5338 is mainly
handled
through
the
I2C/SMBus
interface.
Some
features such as output enable, frequency or phase
adjustments can optionally be pin controlled. The device
has a maskable interrupt pin which can be monitored for
loss of lock or loss of input signal conditions.
The device also provides the option of storing a user
definable clock configuration in its non-volatile memory
(NVM) which becomes the default clock configuration at
power-up. Changes to the default configuration can
always be made through the I2C interface.
The Si5338 brings unprecedented flexibility and easy of
use
to
high
performance
clock
generation
and
distribution applications.
Phase
Frequency
Detector
Loop
Filter
VCO
CLK0A
÷P2
VDDO1
VDDO2
VDDO3
VDDO0
MultiSynth
÷M0
I2C_LSB/PDEC/FDEC
OEB/PINC/FINC
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷P1
IN3
IN2
IN1
÷R1
MultiSynth
÷M1
MultiSynth
÷M2
MultiSynth
÷M3
IN6
IN4
IN5
Osc
MultiSynth
÷N
Control
NVM
(OTP)
÷R0
÷R2
÷R3
Input
Stage
Synthesis
Stage 1
(APLL)
Synthesis
Stage 2
Output
Stage
CLKIN
CLKINB
Control & Memory
SCL
SDA
INTR
FDBK
FDBKB
VDD
ref
fb
RAM
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338N-A00211-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338N-A01659-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338N-A01659-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| Si5338N-A-GM | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C-prgrmmbl clock generatr .16-700 MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338N-A-GMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C Program Clk Gen 0.16-710MHz 4Clk In RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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