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參數(shù)資料
| 型號(hào)： | SI5338N-A00000-GMR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁數(shù)： | 20/34頁 |
| 文件大?。?/td> | 285K |
| 代理商： | SI5338N-A00000-GMR |
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Si5338
Rev. 0.5
27
10
CLK3A
O
Multi
Output Clock A for Channel 3
May be a single-ended output or half of a differential
output with CLK3B being the other differential half.
11
VDDO3
VDD
Supply
Output Clock Supply Voltage
Supply voltage (3.3V, 2.5V, 1.8V, or 1.5V) for CLK3A,B.
A 0.1 F capacitor must be located very close to this pin.
If CLK3 is not used, this pin must be tied to VDD (pin 7,
24).
12
SCL
I
LVCMOS
I2C Serial Clock Input
This is the serial clock input for the I2C bus. This pin
must be pulled-up using a pull-up resistor of at least
1 k
.
13
CLK2B
O
Multi
Output Clock B for Channel 2
May be a single-ended output or half of a differential
output with CLK2A being the other differential half.
14
CLK2A
O
Multi
Output Clock A for Channel 2
May be a single-ended output or half of a differential
output with CLK2B being the other differential half.
15
VDDO2
VDD
Supply
Output Clock Supply Voltage
Supply voltage (3.3V, 2.5V, 1.8V, or 1.5V) for CLK2A,B.
A 0.1 F capacitor must be located very close to this pin.
If CLK2 is not used, this pin must be tied to VDD (pin 7,
24).
16
VDDO1
VDD
Supply
Output Clock Supply Voltage
Supply voltage (3.3V, 2.5V, 1.8V, or 1.5V) for CLK1A,B.
A 0.1 F capacitor must be located very close to this pin.
If CLK1 is not used, this pin must be tied to VDD (pin 7,
24).
17
CLK1B
O
Multi
Output Clock B for Channel 1
May be a single-ended output or half of a differential
output with CLK1A being the other differential half.
18
CLK1A
O
Multi
Output Clock A for Channel 1
May be a single-ended output or half of a differential
output with CLK1B being the other differential half.
19
SDA
I/O
LVCMOS
I2C Serial Data
This is the serial data for the I2C bus. This pin must be
pulled-up using a pull-up resistor of at least 1 k
.
20
VDDO0
VDD
Supply
Output Clock Supply Voltage
Supply voltage (3.3V, 2.5V, 1.8V, or 1.5V) for CLK0A,B.
A 0.1 F capacitor must be located very close to this pin.
If CLK0 is not used, this pin must be tied to VDD (pin 7,
24).
21
CLK0B
O
Multi
Output Clock B for Channel 0
May be a single-ended output or half of a differential
output with CLK0A being the other differential half.
Table 14. Si5338 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5338N-AXXXXXGM | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| SL28540ALCT | OTHER CLOCK GENERATOR, QCC56 |
| SL5504 | 1 CHANNEL TRANSISTOR OUTPUT OPTOCOUPLER |
| SL5582.3S | 1 CHANNEL TRANSISTOR OUTPUT OPTOCOUPLER |
| SLA-360MTT32S | T-1 SINGLE COLOR LED, YELLOW GREEN, 3.1 mm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338N-A00211-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338N-A01659-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338N-A01659-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| Si5338N-A-GM | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C-prgrmmbl clock generatr .16-700 MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338N-A-GMR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 I2C Program Clk Gen 0.16-710MHz 4Clk In RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
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