- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25644 > SI5338N-A00000-GMR (SILICON LABORATORIES) 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 PDF資料下載
參數(shù)資料
| 型號： | SI5338N-A00000-GMR |
| 廠商： | SILICON LABORATORIES |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, MO-220VGGD-8, QFN-24 |
| 文件頁數(shù)： | 10/34頁 |
| 文件大?。?/td> | 285K |
| 代理商： | SI5338N-A00000-GMR |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁
Si5338
18
Rev. 0.5
The second stage of synthesis consist of four additional
highly precise MultiSynth output dividers (M0, M1, M2,
M3) which ultimately determines the output clock
frequencies. Using this two stage technique, the Si5338
can generate four independent output clocks with any
frequency between the range of 5 to 350 MHz and
select ranges up to 710 MHz with 0 ppm accuracy.
3.4. Output Stage
The output stage consists of output selectors, output
dividers, and programmable output drivers as shown in
Figure 6. Output Stage
The output selectors select the clock source for the
output drivers. By default, each output driver is
connected to its own MultiSynth block (e.g. M0 to CLK0,
M1 to CLK1, etc), but other combinations are possible
by reconfiguring the device. Any of the output drivers
can also connect to any of the clocks in the input stage
(osc, ref, refdiv, fb, or fbdiv) effectively bypassing the
synthesis stages. Each of the output drivers can also
connect to the first MultiSynth block (M0) enabling a
fan-out function. This allows the Si5338 to act as a clock
generator, a fanout buffer, or a combination of both in
the same package.
The output dividers (R0, R1, R2, R3) allow another
stage of clock division.These dividers are configurable
as divide by 1 (default), 2, 4, 8, 16, or 32.
The output drivers are configurable to support
common signal formats such as LVPECL, LVDS, HCSL,
CMOS, HSTL, and SSTL. Separate output supply pins
(VDDOn) are available for generating 3.3, 2.5, 1.8, and
1.5 V signal levels. Additionally, the outputs can be
configured to stop high, low, or tri-state when the APLL
has lost lock. Each of the outputs can also be enabled
or disabled through the I2C port.
3.5. Configuring the Si5338
The Si5338 is a highly flexible clock generator which is
entirely configurable through its I2C interface. The
device’s default configuration is stored in non-volatile
memory (NVM) as shown in Figure 7. The NVM is a one
time programmable memory (OTP) which can store a
custom user configuration at power-up. This is a useful
feature for applications that need a clock present at
power-up (e.g. for providing a clock to a processor).
Figure 7. Si5338 Memory Configuration
During a power cycle or a power-on reset (POR) the
contents of the NVM are copied into random access
memory (RAM) which is where the device operates
from. Any changes to the device’s configuration after
power up is made by reading and writing to registers in
the RAM space through the I2C interface.
3.5.1. Configuring the Si5338 by Writing to RAM
The Any Rate Clock Generator Software available from
the Silicon Labs web site (www.silabs.com) provides an
easy to use Graphical User Interface (GUI) to help set
the input configuration, the APLL and MultiSynth
parameters,
output
configuration,
and
other
miscellaneous
features
and
functions.
The
GUI
generates a new register map file which can be written
to RAM through the I2C port. Writing the new
configuration to RAM must be done after every power
cycle or a manual power-on reset (POR) cycle.
CLK0A
VDDO1
VDDO2
VDDO3
VDDO0
CLK0B
CLK1A
CLK1B
CLK2A
CLK2B
CLK3A
CLK3B
÷R1
÷R0
÷R2
÷R3
Output
Stage
From
Synt
hesi
s
S
tage
or
Input
S
tage
Power-Up/POR
NVM
(OTP)
Default
Config
I
2C
RAM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SI5338N-AXXXXXGM | 700 MHz, PROC SPECIFIC CLOCK GENERATOR, QCC24 |
| SL28540ALCT | OTHER CLOCK GENERATOR, QCC56 |
| SL5504 | 1 CHANNEL TRANSISTOR OUTPUT OPTOCOUPLER |
| SL5582.3S | 1 CHANNEL TRANSISTOR OUTPUT OPTOCOUPLER |
| SLA-360MTT32S | T-1 SINGLE COLOR LED, YELLOW GREEN, 3.1 mm |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SI5338N-A00211-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| SI5338N-A01659-GM | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Bulk |
| SI5338N-A01659-GMR | 制造商:Silicon Laboratories Inc 功能描述:CLOCK - Tape and Reel |
| Si5338N-A-GM | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C-prgrmmbl clock generatr .16-700 MHz RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| SI5338N-A-GMR | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 I2C Program Clk Gen 0.16-710MHz 4Clk In RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。