參數(shù)資料
型號(hào): SI5325C-C-GM
廠(chǎng)商: Silicon Laboratories Inc
文件頁(yè)數(shù): 8/62頁(yè)
文件大?。?/td> 0K
描述: IC UP-PROG CLK MULTIPLIER 36-QFN
標(biāo)準(zhǔn)包裝: 490
系列: DSPLL®
類(lèi)型: 時(shí)鐘乘法器
PLL:
輸入: 時(shí)鐘
輸出: CML,CMOS,LVDS,LVPECL
電路數(shù): 1
比率 - 輸入:輸出: 2:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 346MHz
除法器/乘法器: 是/是
電源電壓: 1.71 V ~ 3.63 V
工作溫度: -40°C ~ 85°C
安裝類(lèi)型: 表面貼裝
封裝/外殼: 36-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 36-QFN(6x6)
包裝: 托盤(pán)
Si5325
16
Rev. 0.5
2. Functional Description
The Si5325 is a low jitter, precision clock multiplier for
applications requiring clock multiplication without jitter
attenuation. The Si5325 accepts dual clock inputs
ranging from 10 to 710 MHz and generates two
synchronous clock outputs ranging from 2 kHz to
945 MHz and select frequencies to 1.4 GHz. The device
provides frequency translation across this operating
range. Independent dividers are available for each input
clock and output clock, so the Si5325 can accept input
clocks at different frequencies and it can generate
output clocks at different frequencies. The Si5325 input
clock frequency and clock multiplication ratio are
programmable through an I2C or SPI interface. Silicon
Laboratories
offers
a
PC-based
software
utility,
DSPLLsim, that can be used to determine the optimum
PLL divider settings for a given input frequency/clock
multiplication ratio combination that minimizes phase
noise and power consumption. This utility can be
downloaded from http://www.silabs.com/timing (click on
Documentation).
The Si5325 is based on Silicon Laboratories' third-
generation
DSPLL
technology,
which
provides
frequency synthesis in a highly integrated PLL solution
that eliminates the need for external VCXO and loop
filter components. The Si5325 PLL loop bandwidth is
digitally programmable and supports a range from
150kHz to 1.3MHz. The DSPLLsim software utility can
be used to calculate valid loop bandwidth settings for a
given input clock frequency/clock multiplication ratio.
In the case when the input clocks enter alarm
conditions, the PLL will freeze the DCO output
frequency near its last value to maintain operation with
an internal state close to the last valid operating state.
The Si5325 has two differential clock outputs. The
electrical format of each clock output is independently
programmable to support LVPECL, LVDS, CML, or
CMOS loads. If not required, the second clock output
can be powered down to minimize power consumption.
For system-level debugging, a bypass mode is available
which drives the output clock directly from the input
clock, bypassing the internal DSPLL. The device is
powered by a single 1.8, 2.5, or 3.3 V supply.
2.1. Further Documentation
Consult
the
Silicon
Laboratories
Any-Frequency
Precision Clock Family Reference Manual (FRM) for
detailed information about the Si5325. Additional design
support is available from Silicon Laboratories through
your distributor.
Silicon
Laboratories
has
developed
a
PC-based
software utility called DSPLLsim to simplify device
configuration, including frequency planning and loop
bandwidth selection. The FRM and this utility can be
downloaded from http://www.silabs.com/timing; click on
Documentation.
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