
Si5325
Rev. 0.5
15
Figure 4. Si5325 Typical Application Circuit (I2C Control Mode)
Figure 5. Si5325 Typical Application Circuit (SPI Control Mode)
Si5325
INT_C1B
C2B
RST
CKOUT1+
CKOUT1–
VD
D
GN
D
Serial Data
Serial Clock
Reset
Interrupt/CKIN_1 Invalid Indicator
CKIN_2 Invalid Indicator
Clock Outputs
CKOUT2+
CKOUT2–
SDA
SCL
I
2C Interface
Serial Port Address
A[2:0]
CMODE
Control Mode (L)
CKIN1+
CKIN1–
Input
Clock
Sources*
CKIN2+
CKIN2–
Assumes differential LVPECL termination (3.3 V) on clock inputs.
*Note:
Ferrite
Bead
System
Power
Supply
C3
C2
C1
C4
0.1 F
1 F
0.1 F
100
0.1 F
+
–
0.1 F
100
0.1 F
+
–
130
130
82
82
VDD = 3.3 V
130
130
82
82
VDD = 3.3 V
Si5325
INT_C1B
C2B
SPI Interface
RST
CKOUT1+
CKOUT1–
VD
D
GND
Reset
Interrupt/CLKIN_1 Invalid Indicator
CLKIN_2 Invalid Indicator
CKOUT2+
CKOUT2–
Serial Data Out
Serial Data In
SDO
SDI
Serial Clock
SCLK
Slave Select
SS
CMODE
Control Mode (H)
CKIN1+
CKIN1–
Input
Clock
Sources*
CKIN2+
CKIN2–
Assumes differential LVPECL termination (3.3 V) on clock inputs.
*Note:
Clock Outputs
0.1 F
100
0.1 F
+
–
0.1 F
100
0.1 F
+
–
Ferrite
Bead
System
Power
Supply
C3
C2
C1
C4
0.1 F
1 F
130
130
82
82
VDD = 3.3 V
130
130
82
82
VDD = 3.3 V