參數(shù)資料
型號(hào)： SI5321-G-BC
廠商： Silicon Laboratories Inc
文件頁(yè)數(shù)： 21/34頁(yè)
文件大?。?/td> 0K
描述： IC PREC CLOCK MULTIPLIER 63CBGA
標(biāo)準(zhǔn)包裝： 260
系列： DSPLL®
類型： 時(shí)鐘乘法器
PLL： 是
輸入： LVTTL
輸出： CML
電路數(shù)： 1
比率 - 輸入:輸出： 1:1
差分 - 輸入:輸出： 是/是
頻率 - 最大： 2.8GHz
除法器/乘法器： 是/是
電源電壓： 3.135 V ~ 3.465 V
工作溫度： -20°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 63-CBGA
供應(yīng)商設(shè)備封裝： 63-CBGA（9x9）
包裝： 托盤
其它名稱： 336-1274
Si5321
28
Rev. 2.5
H4
VALTIME
I*
LVTTL*
Clock Validation Time for LOS.
VALTIME sets the clock validation times for recovery
from an LOS alarm condition. When VALTIME is
high, the validation time is approximately 100 ms.
When VALTIME is low, the validation time is approx-
imately 2 ms.
H3
RSTN/CAL
I*
LVTTL*
Reset/Calibrate.
When low, all LVTTL outputs are forced into a high
impedance state, the DSPLL is forced out-of-lock,
and the device control logic is reset.
A low-to-high transition on RSTN/CAL initializes all
digital logic to a known condition and initiates self-
calibration of the DSPLL. At the completion of self-
calibration, the DSPLL begins to lock to the selected
clock input signal and begins to drive out the output
clock signal onto the CLKOUT pins.
F8
LOS
O
LVTTL
Loss-of-Signal (LOS) Alarm for CLKIN.
Active high output indicates that the Si5321 has
detected missing pulses on the input clock signal.
The LOS alarm is cleared after either 100 ms or 13 s
of a valid CLKIN clock input, depending on the set-
ting of the VALTIME input.
D8
DH_ACTV
O
LVTTL
Digital Hold Mode Active.
Active high output indicates that the DSPLL is in
digital hold mode. Digital hold mode locks the
current state of the DSPLL and forces the DSPLL to
continue generation of the output clock with no
additional phase or frequency information from the
input clock.
E8
CAL_ACTV
O
LVTTL
Calibration Mode Active.
This output is driven high during the DSPLL self-cal-
ibration and the subsequent initial lock acquisition
period.
C2
VSEL33
I*
LVTTL*
Reserved.
This pin must be tied to VDD33 directly for normal
operation.
D3–D5,
E3–E5
VDD33
VDD
Supply
3.3 V Supply.
3.3 V power is applied to the VDD33 pins. Typical
supply bypassing/decoupling for this configuration is
indicated in the typical application diagram for 3.3 V
supply operation.
Table 10. Si5321 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTTL inputs on the Si5321 device have an internal pulldown mechanism that causes the input to default to a
logic low state if the input is not driven from an external source.
相關(guān)PDF資料
PDF描述
SI5321-H-BL IC CLOCK MULT SONET/SDH 63-PBGA
SI5322-B-GM IC PREC CLOCK MULTIPLIER 36QFN
SI5323-B-GM IC MULTIPLIER/ATTENUATOR 36QFN
SI5325A-C-GM IC UP-PROG CLK MULTIPLIER 36-QFN
SI5326A-C-GM IC ANY-RATE MULTI/ATTEN 36-QFN
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SI5321-G-XC2 制造商:Silicon Laboratories Inc 功能描述:
Si5321-H-BL 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
Si5321-H-GL 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 SONET/SDH Precisn Clock Multiplr RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56
SI5321-H-ZL2 制造商:Silicon Laboratories Inc 功能描述:
Si5321-XLNX-DC 功能描述:子卡和OEM板 Silabs/Xilinx Ref Design RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*