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參數(shù)資料
| 型號： | SI5320-X-BC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| 中文描述： | SONET / SDH的精密時鐘倍頻集成電路 |
| 文件頁數(shù)： | 27/34頁 |
| 文件大?。?/td> | 538K |
| 代理商： | SI5320-X-BC |
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Si5320
Rev. 2.3
27
B1
C1
BWSEL[0]
BWSEL[1]
I*
LVTTL
Bandwidth Select.
BWSEL[1:0] pins set the bandwidth of the loop filter
within the DSPLL to 6400, 3200, 1600, or 800 Hz as
indicated below.
00 = 3200 Hz
01 = 1600 Hz
10 = 800 Hz
11 = 6400 Hz
Note:
The loop filter bandwidth will be twice the value
indicated when DBLBW is set high.
E8
CAL_ACTV
O
LVTTL
Calibration Mode Active.
This output is driven high during the DSPLL self-cal-
ibration and the subsequent initial lock acquisition
period.
H4
VALTIME
I*
LVTTL
Clock Validation Time for LOS.
VALTIME sets the clock validation times for recovery
from an LOS alarm condition. When VALTIME is
high, the validation time is approximately
13 seconds. When VALTIME is low, the validation
time is approximately 100 ms.
B2, B3, B6,
B7, C8
RSVD_GND
—
LVTTL
Reserved—GND.
This pin must be tied to GND for normal operation.
A4–8, B5, B8
RSVD_NC
—
LVTTL
Reserved—No Connect.
This pin must be left unconnected for normal
operation.
C2
VSEL33
I*
LVTTL
Select 3.3 V V
DD
Supply.
This is an enable pin for the internal regulator. To
enable the regulator, connect this pin to the V
DD33
pins.
D3–D5,
E3–E5
V
DD33
V
DD
Supply
3.3 V Supply.
3.3 V power is applied to the V
DD33
pins. Typical
supply bypassing/decoupling for this configuration is
indicated in the typical application diagram for 3.3 V
supply operation.
D6, D7, E6,
E7, F3–F7
V
DD25
V
DD
Supply
2.5 V Supply.
These pins provide a means of connecting the
compensation network for the on-chip regulator.
Table 11. Si5320 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
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