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參數(shù)資料
| 型號： | SI5320-X-BC |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | SONET/SDH PRECISION CLOCK MULTIPLIER IC |
| 中文描述： | SONET / SDH的精密時(shí)鐘倍頻集成電路 |
| 文件頁數(shù)： | 25/34頁 |
| 文件大?。?/td> | 538K |
| 代理商： | SI5320-X-BC |
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Si5320
Rev. 2.3
25
F1
G1
H1
INFRQSEL[0]
INFRQSEL[1]
INFRQSEL[2]
I*
LVTTL
Input Frequency Range Select.
Pins(INFRQSEL[2:0]) select the frequency range for
the input clock, CLKIN. (See Table 3 on page 7.)
000 = Reserved.
001 = 19 MHz range.
010 = 38 MHz range.
011 = 77 MHz range.
100 = 155 MHz range.
101 = 311 MHz range.
110 = 622 MHz range.
111 = Reserved.
F8
LOS
O
LVTTL
Loss-of-Signal (LOS) Alarm for CLKIN.
Active high output indicates that the Si5320 has
detected missing pulses on the input clock signal.
The LOS alarm is cleared after either 100 ms or
13 seconds of a valid CLKIN clock input, depending
on the setting of the VALTIME input.
D8
DH_ACTV
O
LVTTL
Digital Hold Mode Active.
Active high output indicates that the DSPLL is in
digital hold mode. Digital hold mode locks the
current state of the DSPLL and forces the DSPLL to
continue generation of the output clock with no
additional phase or frequency information from the
input clock.
H3
RSTN/CAL
I*
LVTTL
Reset/Calibrate.
When low, the internal circuitry enters into the reset
mode and all LVTTL outputs are forced into a high-
impedance state. Also, the CLKOUT+ and
CLKOUT– pins are forced to a nominal CML logic
LOW and HIGH respectively. This feature is useful
for in-circuit test applications.
A low-to-high transition on RSTN/CAL initializes all
digital logic to a known condition, enables the device
outputs, and initiates self-calibration of the DSPLL.
Upon completion of self-calibration, the DSPLL
begins to lock to the selected clock input signal.
Table 11. Si5320 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
*Note:
The LVTLL inputs on the Si5320 device have an internal pulldown mechanism that causes these inputs to default to a
logic low state if the input is not driven from an external source.
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