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參數(shù)資料
| 型號： | SI5100-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 195PBGA |
| 標準包裝： | 119 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 195-LBGA |
| 供應商設備封裝： | 195-BGA（15x15） |
| 包裝： | 托盤 |
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Si5100
28
Rev. 1.5
H4
REFRATE
I
LVTTL
Reference Clock Rate Select.
The REFRATE input sets the frequency for the
REFCLK input. When REFRATE is set high, the
REFCLK frequency is 1/16th the serial data rate
(nominally 155 MHz). When REFRATE is set
low, the REFCLK frequency is 1/32nd the serial
data rate (nominally 78 MHz).
The REFRATE input has no effect when the
REFSEL input is set low.
Note: This input has an internal pullup.
L12
REFSEL
I
LVTTL
Reference Clock Selection.
This input selects the reference clock source to
be used by the Si5100 transmitter and receiver.
The reference clock sets the operating fre-
quency of the Si5100 transmit CMU, which is
used to generate the high-speed transmit clock
TXCLKOUT. The reference clock is also used by
the Si5100 receiver CDR to center the PLL dur-
ing lock acquisition, and as a reference for deter-
mination of the receiver lock status.
When REFSEL = 0, the low-speed data input
clock, TXCLK16IN, is used as the reference
clock. When REFSEL = 1, the reference clock
provided on REFCLK is used.
Note: This input has an internal pullup.
G4
RESET
I
LVTTL
Device Reset.
Forcing this input low for a at least 1
s causes a
device reset. For normal operation, this pin
should be held high.
Note: This input has an internal pullup.
C6–7, D3, K4,
L4, M8, M11
RSVD_GND
Reserved Tie to Ground.
Must be connected directly to GND for proper
operation.
C10
RXAMPMON
O
Analog
Receiver Amplitude Monitor.
The RXAMPMON output provides an analog
output signal that is proportional to the input
signal
amplitude.
See
Equation 1 for
the
relationship between the RXAMPMON output
and RXDIN input. This signal is active when
SLICEMODE is asserted.
A2
A3
RXCLK1+
RXCLK1–
OLVDS
Differential Receiver Clock Output 1.
The clock recovered from the signal present on
RXDIN is divided down to the parallel output
word rate and output on RXCLK1. In the
absence of data, a stable clock on RXCLK1 can
be maintained by asserting LTR.
Pin Number(s)
Name
I/O
Signal Level
Description
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