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參數(shù)資料
| 型號(hào)： | SI5100-H-GL |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 14/40頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX SONET/SDH LP HS 195PBGA |
| 標(biāo)準(zhǔn)包裝： | 119 |
| 系列： | SiPHY™ |
| 類型： | 收發(fā)器 |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | SONET/SDH |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 195-LBGA |
| 供應(yīng)商設(shè)備封裝： | 195-BGA（15x15） |
| 包裝： | 托盤(pán) |
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Si5100
Rev. 1.5
21
9. Line Loopback
The Si5100 provides a line loopback mode that
establishes a loopback path from the high-speed
receive input to the high-speed transmit output. This
provides a mechanism for looping back the high-speed
clock and data recovered from RXDIN to the transmit
data output, TXDOUT, and clock, TXCLKOUT. This
mode is enabled when the LLBK input is set low.
Note: Setting both DLBK and LLBK low simultaneously is not
supported.
10. Bias Generation Circuitry
The Si5100 uses two external resistors, RXREXT and
TXREXT, to set internal bias currents for the receive
and transmit sections of the device, respectively. The
external resistors allow precise generation of bias
currents,
which
can
significantly
reduce
power
consumption. The bias generation circuitry requires two
3.09 k
(1%) resistors each connected between
RXREXT and GND and between TXREXT and GND.
11. Reference Clock
The Si5100 supports operation with one of two possible
reference clock sources. In the first configuration, an
external reference clock is connected to the REFCLK
input. The second configuration uses the parallel data
clock, TXCLK16IN, as the reference clock source. The
REFSEL input is used to select whether the REFCLK or
the TXCLK16IN input are used as the reference clock.
When REFCLK is selected as the reference clock
source (REFSEL = 1), two possible reference clock
frequencies
are
supported.
The
reference
clock
frequency provided on the REFCLK input can be either
1/16th or 1/32th the desired transceiver data rate. The
REFCLK frequency is selected using the REFRATE
input.
The TXCLK16IN clock frequency is equal to either 1/4th
or 1/16th the transceiver data rate depending on the
state of the MODE16 input. When TXCLK16IN is
selected as the reference clock source (REFSEL = 0),
the REFRATE input has no effect.
The CMU in the Si5100’s transmit section multiplies the
provided reference up to the serial transmit data rate.
When the CMU has achieved lock with the selected
reference, the TXLOL output is deasserted (driven
high).
The CDR in the receive section of the Si5100 uses the
selected reference clock to center the receiver PLL
frequency in order to speed lock acquisition. When the
receive CDR locks to the data input, the RXLOL signal
is deasserted (driven high).
12. Reset
The Si5100 is reset by holding the RESET pin low for at
least 1 s. When RESET is asserted, the input FIFO
pointers are reset and the digital control circuitry is
initialized.
When RESET transitions high to start normal operation,
the transmit CMU calibration is performed.
13. Transmit Differential Output
Circuitry
The Si5100 utilizes a current-mode logic (CML)
architecture to drive the high-speed serial output clock
and data on TXCLKOUT and TXDOUT. An example of
output termination with ac coupling is shown in Figure 9.
In applications with direct dc coupling, the 0.1
F
capacitors can be omitted. The differential peak-to-peak
voltage swing of the CML architecture is listed in
14. Internal Pullups and Pulldowns
On-chip 30 k
resistors are used to individually set the
LVTTL inputs if these inputs are left unconnected. The
specific default state of each input is enumerated in 17.
15. Power Supply Filtering
The transmitter-generated jitter is most sensitive to
power supply noise below its PLL loop-bandwidth
(BWSEL setting). The power supply noise of interest is
bounded between the SONET/SDH generated jitter
specification of 12 kHz (for 2.48832 Gbps) and the PLL
loop-bandwidth. Integrated supply noise from 1/10th the
SONET/SDH specification (1.2 kHz) to 10x the loop-
bandwidth should be suppressed to a level appropriate
for each design. Below the PLL loop-bandwidth, the
typical
generated
jitter
due
to
supply
noise
is
approximately 2.5 mUIpp per 1 mVrms; this parameter
can be used as a guideline for calculating the output
jitter and supply filtering requirements. The receiver
does not place additional power supply constraints
beyond those listed for the transmitter.
Please
contact
Silicon
Laboratories’
applications
engineering for recommendations on bypass capacitors
and their placement.
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