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參數(shù)資料
| 型號(hào)： | Si5013-X-GM |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | OC-12/3, STM-4/1 SONET/SDH CDR IC WITH LIMITING AMPLIFIER |
| 中文描述： | 的OC - 12 / 3接口，STM - 4 / 1的SONET / SDH的CDR集成電路限幅放大器 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大?。?/td> | 153K |
| 代理商： | SI5013-X-GM |
Si5013
14
Rev. 1.4
R1 may be chosen to provide a range of hysteresis from
3 to 8 dB where a nominal value of 800
hysteresis level to approximately 6 dB. Use a value of
500
or 1000
for R1 to provide 3 dB or 8 dB of
hysteresis, respectively.
Hysteresis is defined as the ratio of the LOS deassert
level (LOSD) and the LOS assert level (LOSA). The
hysteresis in decibels is calculated as 20log(LOSD/
LOSA).
4.9. Bit Error Rate (BER) Detection
The Si5013 uses a proprietary Silicon Laboratories
algorithm to generate a bit error rate (BER) alarm on the
BER_ALM pin if the observed BER is greater than a
user programmable threshold. Bit error detection relies
on the input data edge timing; edges occurring outside
of the expected event window are counted as bit errors.
The BER threshold is programmed by applying a
voltage to the BER_LVL pin between 500 mV and
2.25 V corresponding to a BER of approximately 10
–10
and 10
–6
, respectively. The voltage present on
BER_LVL maps to the BER as follows: log10(BER) =
(4 x BER_LVL) –13. (BER_LVL is in volts; BER is in bits
per second.)
4.10. Data Slicing Level
The Si5013 provides the ability to externally adjust the
slicing level for applications that require bit error rate
(BER) optimization. Adjustments in slicing level of
±15 mV (relative to the internally set input common
mode voltage) are supported. The slicing level is set by
applying a voltage between 0.75 and 2.25 V to the
SLICE_LVL input. The voltage present on SLICE_LVL
maps to the slicing level as follows:
adjusts the
where V
SLICE
is the slicing level, and V
SLICE_LVL
is the
voltage applied to the SLICE_LVL pin.
When SLICE_LVL is driven below 500 mV, the slicing
level adjustment is disabled, and the slicing level is set
to the cross-point of the differential input signal.
4.11. PLL Performance
The PLL implementation used in the Si5013 is fully
compliant with the jitter specifications proposed for
SONET/SDH equipment by Bellcore GR-253-CORE,
Issue 3, September 2000 and ITU-T G.958.
4.11.1. Jitter Tolerance
The Si5013’s tolerance to input jitter exceeds that of the
Bellcore/ITU mask shown in Figure 8. This mask
defines the level of peak-to-peak sinusoid jitter that
must be tolerated when applied to the differential data
input of the device.
Figure 8. Jitter Tolerance Specification
4.11.2. Jitter Transfer
The
Si5013
exceeds
specifications related to SONET/SDH jitter transfer.
Jitter transfer is defined as the ratio of output signal jitter
to input signal jitter as a function of jitter frequency.
These measurements are made with an input test signal
that is degraded with sinusoidal jitter whose magnitude
is defined by the mask in Figure 9.
all
relevant
Bellcore/ITU
Figure 9. Jitter Transfer Specification
V
SLICE
V
-------------------------------------------------------
1.5 V
–
=
15
1.5
0.15
f0
f1
f2
f3
ft
Sinusoidal
Input
Jitter (UI
PP
)
Frequency
Slope = 20 dB/Decade
F0
(Hz)
10
10
F1
(Hz)
30
30
F2
(kHz)
300
300
SONET
Data Rate
OC-12
OC-3
F3
(kHz)
25
6.5
Ft
(kHz)
250
65
0.1 dB
Jitter
Transfer
Fc
Frequency
20 dB/Decade
Slope
Fc
(kHz)
500
130
SONET
Data Rate
OC-12
OC-3
Acceptable
Range
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