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參數(shù)資料
| 型號(hào)： | SI5010-EVB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁(yè)數(shù)： | 7/20頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR SI5010 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 主要目的： | 計(jì)時(shí)，時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR） |
| 已用 IC / 零件： | SI5010 |
| 已供物品： | 板 |
| 其它名稱(chēng)： | 336-1121 |
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Si5010
Rev. 1.4
15
12
13
DOUT–
DOUT+
OCML
Differential Data Output.
The data output signal is a retimed version of the
data recovered from the signal present on DIN. It is
phase aligned with CLKOUT and is updated on the
rising edge of CLKOUT.
15
PWRDN/CAL
I
LVTTL
Powerdown.
To shut down the high-speed outputs and reduce
power consumption, hold this pin high. For normal
operation, hold this pin low.
Calibration.
To initiate an internal self-calibration, force a
high-to-low transition on this pin. (See "4.2. PLL
Note: This input has a weak internal pulldown.
16
17
CLKOUT–
CLKOUT+
OCML
Differential Clock Output.
The output clock is recovered from the data signal
present on DIN. In the absence of data, the output
clock is derived from REFCLK.
19
RATESEL
I
LVTTL
Data Rate Select.
This pin configures the onboard PLL for clock and
data recovery at one of two user selectable data
rates. See Table 7 for configuration settings.
Note: This input has a weak internal pulldown.
20
NC
No Connect.
This pin should be tied to ground.
Table 8. Si5010 Pin Descriptions (Continued)
Pin #
Pin Name
I/O
Signal Level
Description
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