參數(shù)資料
型號(hào): SI5010-EVB
廠商: Silicon Laboratories Inc
文件頁(yè)數(shù): 5/20頁(yè)
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR SI5010
標(biāo)準(zhǔn)包裝: 1
主要目的: 計(jì)時(shí),時(shí)鐘和數(shù)據(jù)恢復(fù)(CDR)
已用 IC / 零件: SI5010
已供物品:
其它名稱: 336-1121
Si5010
Rev. 1.4
13
4.11. Differential Output Circuitry
The Si5010 utilizes a current mode logic (CML) architecture to output both the recovered clock (CLKOUT) and data
(DOUT). An example of output termination with ac coupling is shown in Figure 9. In applications in which direct dc
coupling is possible, the 0.1 F capacitors may be omitted. The differential peak-to-peak voltage swing of the CML
architecture is listed in Table 2 on page 6.
Figure 9. Output Termination for DOUT and CLKOUT (AC Coupled)
DOUT–,
CLKOUT–
50
Ξ
50
Ξ
0.1
ΞF
0.1
ΞF
Zo = 50
Ξ
Zo = 50
Ξ
Si5010
VDD
100
Ξ
100
Ξ
VDD
DOUT+,
CLKOUT+
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