參數(shù)資料
型號: SI5010-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 1/20頁
文件大?。?/td> 0K
描述: BOARD EVALUATION FOR SI5010
標(biāo)準(zhǔn)包裝: 1
主要目的: 計時,時鐘和數(shù)據(jù)恢復(fù)(CDR)
已用 IC / 零件: SI5010
已供物品:
其它名稱: 336-1121
Rev. 1.4 6/08
Copyright 2008 by Silicon Laboratories
Si5010
OC-12/3, STM-4/1 SONET/SDH CLOCK AND DATA RECOVERY IC
Features
Complete CDR solution includes the following:
Applications
Description
The Si5010 is a fully-integrated low-power clock and data recovery (CDR)
IC designed for high-speed serial communication systems. It extracts
timing information and data from a serial input at OC-12/3 or STM-4/1 data
rates. DSPLL technology eliminates sensitive noise entry points thus
making the PLL less susceptible to board-level interaction and helping to
ensure optimal jitter performance in the application.
The Si5010 represents an industry-leading combination of low-jitter,
low-power, and small size for high-speed CDRs. It operates from a single
2.5 V supply over the industrial temperature range (–40 to 85 °C).
Functional Block Diagram
Supports OC-12/3, STM-4/1
Low power, 293 mW (TYP OC-12)
Small footprint: 4x4 mm
DSPLL eliminates external loop
filter components
3.3 V tolerant control inputs
Exceeds All SONET/SDH jitter
specifications
Jitter generation
1.6 mUIrms (typ)
Device powerdown
Loss-of-lock indicator
Single 2.5 V supply
SONET/SDH/ATM routers
Add/drop multiplexers
Digital cross connects
Board level serial links
SONET/SDH test equipment
Optical transceiver modules
SONET/SDH regenerators
DSPLLTM
Phase-Locked
Loop
Retim er
BUF
DIN+
DIN–
REXT
LOL
2
REFCLK+
REFCLK–
RATESEL
2
DOUT+
DOUT–
CLKOUT+
CLKOUT–
PW RDN/CAL
2
Bias
Ordering Information:
Pin Assignments
Si5010
GND
Pad
Connection
15
14
13
12
11
PWRDN/CAL
DOUT+
VDD
DOUT–
VDD
1
2
3
4
5
VDD
GND
REFCLK–
REXT
REFCLK+
20
19
18
17
16
NC
R
AT
E
SEL
CLK
O
UT
CLK
O
UT
+
GN
D
6
7
8
9
10
LOL
GND
DI
N
+
DI
N
VD
D
Top View
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