DD = 2.7 to 3.6 V," />
參數(shù)資料
型號: SI4136M-EVB
廠商: Silicon Laboratories Inc
文件頁數(shù): 31/34頁
文件大小: 0K
描述: BOARD EVALUATION FOR SI4136
標準包裝: 1
類型: 合成器
適用于相關產(chǎn)品: SI4136
已供物品: 板,CD
其它名稱: 336-1119
Si4136/Si4126
6
Rev. 1.41
Figure 1. SCLK Timing Diagram
Table 4. Serial Interface Timing
(V
DD = 2.7 to 3.6 V, TA = –40 to 85 °C)
Parameter1
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Cycle Time
tclk
40
ns
SCLK Rise Time
tr
50
ns
SCLK Fall Time
t
f
50
ns
SCLK High Time
th
10
ns
SCLK Low Time
tl
10
ns
SDATA Setup Time to SCLK
2
t
su
5
ns
SDATA Hold Time from SCLK
2
thold
0
ns
SEN
to SCLKDelay Time2
ten1
10
ns
SCLK
to SENDelay Time2
t
en2
12
ns
SEN
to SCLKDelay Time2
ten3
12
ns
SEN Pulse Width
tw
10
ns
Notes:
1. All timing is referenced to the 50% level of the waveform, unless otherwise noted.
2. Timing is not referenced to 50% level of the waveform. See Figure 2.
SCLK
80%
50%
20%
tr
tf
t
h
t
l
t
clk
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