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參數(shù)資料
| 型號： | SH3001IMLTRT |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | REAL TIME CLOCK, QCC16 |
| 封裝： | 3 X 3 MM, 0.90 MM HEIGHT, LEAD FREE, MLP-16 |
| 文件頁數(shù)： | 3/20頁 |
| 文件大小： | 788K |
| 代理商： | SH3001IMLTRT |
SH3001 MicroBuddy
SYSTEM MANAGEMENT
Copyright 2002-2005 Semtech Corporation
11
V1.15
www.semtech.com
IO/INT
timing
scenarios
1.
INT
disabled,
uP
initiates
write
access.
Active
high
interrupt.
uBuddyIOOut
uPIOOut
A0
A4
XXX
D0
D7
...
CombinedIO
A0
A4
XXX
D0
D7
...
2.
INT
active
(high),
uP
initiates
write
access
uBuddyIOOut
uPIOOut
CombinedIO
XXX
State
Idle
Pre-
start
Start
Post-
Start
A0
A4
Guard0
D0
D7
...
Guard1
Idle
XXX
State
If
the
interrupt
did
not
get
cleared,
then
it
will
activate
again
here
4.
INT
disabled,
uP
initiates
read
access
uBuddyIOOut
uPIOOut
A0
A4
XXX
...
CombinedIO
A0
A4
XXX
D0
D7
...
State
Idle
Pre-
start
Start
Post-
Start
A0
A4
Guard0
D0
D7
...
Guard2
Idle
D0
D7
...
P0
P1
P0
P1
P0
P1
P0
P1
P0
P1
P0
P1
ACK0
ACK1
ACK0
ACK1
ACK0
ACK1
RW0
RW1
RW2
A0
A4
XXX
D0
D7
...
A0
A4
XXX
D0
D7
...
XXX
Pre-
start
Start
Post-
Start
A0
A4
Guard0
D0
D7
...
Guard1
XXX
P0
P1
P0
P1
P0
P1
ACK0
ACK1
ACK0
ACK1
RW0
RW1
RW2
ACK0
ACK1
Guard2
Guard3
Guard2
Guard3
Pendin
g-start
IN
T
Idle
Pendin
g-start
IN
T
3.
INT
active
(low),
uP
initiates
write
access
uBuddyIOOut
uPIOOut
CombinedIO
State
If
the
interrupt
did
not
get
cleared,
then
it
will
activate
again
here
A0
A4
XXX
D0
D7
...
A0
A4
XXX
D0
D7
...
XXX
Pre-
start
Start
Post-
Start
A0
A4
Guard0
D0
D7
...
Guard1
XXX
P0
P1
P0
P1
P0
P1
ACK0
ACK1
ACK0
ACK1
RW0
RW1
RW2
Guard2
Guard3
Pendin
g-start
IN
T
Idle
Pendin
g-start
IN
T
ACK0
ACK1
RW0
RW1
RW2
Guard3
Figure 4: Serial Communication Timing Diagram
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