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參數(shù)資料
| 型號： | SH3001IMLTRT |
| 元件分類： | 時鐘/數(shù)據(jù)恢復(fù)及定時提取 |
| 英文描述： | REAL TIME CLOCK, QCC16 |
| 封裝： | 3 X 3 MM, 0.90 MM HEIGHT, LEAD FREE, MLP-16 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 788K |
| 代理商： | SH3001IMLTRT |
SH3001 MicroBuddy
SYSTEM MANAGEMENT
Copyright 2002-2005 Semtech Corporation
10
V1.15
www.semtech.com
Interrupt and Serial Interface
A single line is used to convey bi-directional
information between the SH3001 and the processor, and
as the interrupt line to the processor.
The polarity of the interrupt signal is programmable.
The SH3001 and the host microcontroller
communicate using a single wire, bi-directional
asynchronous serial interface. The bit rate is
automatically determined by the SH3001. . At the
fastest possible rate, a read or write access of a single
byte from the register bank takes 5 s.
The SH3001 contains 36 addressable registers
located at 0x00–0x1F. Some of these registers are
accessed through a page operation. Pin 14, IO/Int, is
the serial communications interface and interrupt output
pin. This pin is internally weakly pulled to the opposite of
the programmed interrupt polarity. For example, if
interrupt is programmed to be active low, this pin is
weakly pulled to VDD when inactive.
As shown in Figure 4, the SH3001 and the host
communicate with serial data streams. The host always
initiates communication. A data stream consists of the
following (in this order):
3-bit start field
3-bit read/write code
5-bit address field
1 guard bit
8-bit data field
2 parity bits
Plus, for write streams only:
1 guard bit
2 acknowledge (ACK) bits
The 3-bit start field (1,0,1 or 0,1,0, depending on
interrupt polarity) uses the middle bit to determine the bit
period of the serial data stream.
The 3-bit read/write code consists of 1,1,0 for a
read, or 0,1,1 for a write. This protects against early
glitches that might otherwise put the interface into an
invalid read or write access mode.
The 5-bit address field contains the address of the
register.
A single guard bit gives the interface a safe period in
which to change data direction. The value of a guard bit
does not matter.
The 8-bit data field is written to (read from) the
register.
Two parity bits: The first parity bit is high when there
are an odd number of bits in the read/write, address and
data fields; the second parity bit is the inverse of the first.
For write streams only, a guard bit is appended to
the stream (to allow safe turnaround), and then two
acknowledge bits, which are a direct copy of the parity
bits, are driven back to the host to indicate a successful
write access.
Two guard bits are appended to the end of the
access stream (read or write). The host can not start the
next access before receiving these bits.
The interface is self-timed based on the duration of
the start bit field, and communication can take place
whenever CLKOUT is active, either at 32.768 kHz or at a
higher frequency. If the host microcontroller is running
synchronously to the CLKOUT generated by the SH3001
(which should generally be the case), then a minimum of
4 CLKOUT cycles per bit are required to maintain
communication integrity. If the host’s serial interface is
asynchronous to CLKOUT, then a minimum of 52 cycles
per bit are necessary. A maximum of 1024 CLKOUT
cycles per bit field is supported.
Table 2 displays the minimum and maximum bit
periods for the serial communications for CLKOUT
frequencies of 16 MHz, 8 MHz, and 2 MHz.
Table 2: Minimum/Maximum Serial Bit Timing
CLKOUT
Frequency
Minimum Bit
Period
(host
synchronous
to
CLKOUT)
Minimum Bit
Period
(host
asynchronous
to
CLKOUT)
Maximum Bit
Period
16 MHz
250 ns
3.25
s
63.9
s
8 MHz
500 ns
6.5
s
127
s
2 MHz
2
s
26
s
511
s
Interrupt Interface
The serial communications line to the SH3001 (Pin
14, IO/Int) also serves as the interrupt to the host
microcontroller. The polarity of the interrupt is software
programmable using the interrupt polarity bit (bit 6) of the
IPol_RCtune register (R0x11). This pin is asserted for
four cycles of CLKOUT, and then returns to the inactive
state.
The interrupt line is used by the Periodic
Interrupt/Wake-up Timer to interrupt the host when it
reaches its end of count.
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