參數(shù)資料
型號: SED1336F
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Controller ICs
中文描述: LCD控制器芯片
文件頁數(shù): 84/148頁
文件大?。?/td> 388K
代理商: SED1336F
S-MOS Systems, Inc. 2460 North First Street San Jose, CA 95131 Tel: (408) 922-0200 Fax: (408) 922-0238
84
268-0.4
5.0 Display Control Functions
5.2.3
5.2.3 Display Scan Timing
Figure 44 shows the basic timing of the SED1330F/
1335F/1336F. One display memory read cycle takes
nine periods of the system clock,
φ
0 (f
OSC
). This cycle
repeats (C/R + 1) times per display line.
When reading, the display memory pauses at the end
of each line for (TC/R – C/R) display memory read
cycles, though the LCD drive signals are still gener-
ated. TC/R may be set to any value within the con-
straints imposed by C/R, f
OSC
, f
FR
, and the size of the
LCD panel, and it may be used to fine tune the frame
frequency. The microprocessor may also use this
pause to access the display memory data.
Frame
period
Display period
Divider frequency
period
TC/R
C/R
O
R
O
R
O
O
R
R
Line 1
2
3
(L/F)
LP
T0
T1
T2
Display read cycle interval
Graphics read interval
Character read interval
Graphics generator
read interval
φ
0
VCE
VA
Figure 52. Display memory basic read cycle
Note:
The divider adjustment interval (R) applies to both the upper and lower screens even if W/S = 1. In this case, LP is active
only at the end of the lower screen’s display interval.
Figure 53. Relationship between TC/R and C/R
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