參數資料
型號: SED1336F
廠商: Electronic Theatre Controls, Inc.
英文描述: LCD Controller ICs
中文描述: LCD控制器芯片
文件頁數: 70/148頁
文件大?。?/td> 388K
代理商: SED1336F
S-MOS Systems, Inc. 2460 North First Street San Jose, CA 95131 Tel: (408) 922-0200 Fax: (408) 922-0238
70
268-0.4
4.5.4.2 SED1336F
Signal
Symbol
Parameter
V
DD
= 4.5 to 5.5V V
DD
= 3.0 to 4.5V
min
max
100
Unit
Condition
min
125
max
EXT
φ
0
t
C
Clock period
VCE HIGH-level pulse-
width
VCE LOW-level pulse-
width
Write cycle time
Address hold time from
falling edge of VCE
Address setup time to
falling edge of VCE
Address hold time from
rising edge of VCE
Address setup time to
falling edge of VWR
Address hold time from
rising edge of VWR
Write setup time to falling
edge of VCE
Write hold time from fall-
ing edge of VCE
Data input setup time to
falling edge of VCE
Data input hold time
from falling edge of VCE
Data hold time from
rising edge of VWR
ns
t
W
t
C
– 50
t
C
– 50
ns
VCE
t
CE
2t
C
– 30
2t
C
– 30
ns
t
CYW
3t
C
3t
C
ns
t
AHC
2t
C
– 30
2t
C
– 40
ns
t
ASC
t
C
– 70
t
C
– 100
ns
VA0 to
VA15
t
CA
0
0
ns
t
AS
0
0
ns
t
AH2
10
10
ns
t
WSC
t
C
– 80
t
C
– 110
ns
VWR
t
WHC
2t
C
– 20
2t
C
– 20
ns
t
DSC
t
C
– 85
t
C
– 120
ns
VD0 to
VD7
t
DHC
2t
C
– 30
2t
C
– 30
ns
t
DH2
5
50
5
50
ns
Note:
VD0 to VD7 are latching input/outputs. While the bus is high impedance, VD0 to VD7 retain the write data until the data read
from the memory is placed on the bus.
T
a
= –20 to 75
°
C
CL = 100
pF
4.0 Specifications
4.5.4.2
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