參數(shù)資料
型號: SDE2526
廠商: SIEMENS AG
英文描述: Nonvolatile Memory 2-Kbit E2PROM with I2C Bus Interface with Extended Temperature Range
中文描述: 非易失性內(nèi)存2與I2C總線接口與千位E2PROM的擴展溫度范圍
文件頁數(shù): 2/10頁
文件大小: 232K
代理商: SDE2526
SDE 2526
Semiconductor Group
83
The transition on SDA from "1" to "0" is a start condition, the transition from "0" to "1" is a stop
condition. During a data transfer the information on the data bus will only change while the clock line
SCL is "0". The information on SDA is valid as long as SCL is "1".
In conjunction with an
I
2
C Bus system, the memory component can operate as a receiver and as a
transmitter (slave receiver or slave transmitter). Between a start and stop condition, information is
always transmitted in byte-organized form. Between the falling edge of the eighth clock pulse and
a ninth acknowledge clock pulse, the memory component sets the SDA-line to low as a confirmation
of reception, if the chip select conditions have been met. During the output of data, the data output
of the memory is high in impedance during the ninth clock pulse (acknowledge master).
The signal timing required for the operation of the
I
2
C Bus is summarized in
figure 2
.
Control Functions of the
I
2
C Bus
The memory component is controlled by the controller (master) via the
I
2
C Bus in two operating
modes: read-out cycle, and reprogramming cycle, including erase and write to a memory address.
In both operating modes, the controller, as transmitter, has to provide 3 bytes and an additional
acknowledge clock pulse to the bus after the start condition. During a memory read, at least nine
additional clock pulses are required to accept the data from the memory and the acknowledge
master, before the stop condition may follow. In the case of programming, the active programming
process is only started by the stop condition after data input (
see figure 3
).
The chip select word contains the 3 chip select bits CS0, CS1 and CS2, thus allowing 8 memory
chips to be connected in parallel. Chip select is achieved when the three control bits logically
correspond to the selected conditions at the select inputs.
Check for End of Programming or Abortion of Programming Process
If the chip is addressed during active reprogramming by entering CS/E, the programming process
is terminated. If, however, it is addressed by entering CS/A, the entry will be ignored. Only after
programming has been terminated will the chip respond to CS/A. This allows the user to check
whether the end of the programming process has been reached (
see figure 3
).
Memory Read
After the input of the first two control words CS/E and WA, a resetting of the start condition and the
input of the third control word CS/A, the memory is set ready to read. During acknowledge clock
nine, the memory information is transferred in parallel mode to the shift register. Subsequent to the
falling edge of the acknowledge clock, the data output is low impedance and the first data bit can be
sampled (
see figure 4
).
With every shift clock, an additional bit reaches the output. After reading a byte, the internal address
counter is automatically incremented when the master receiver switches the data line to "low"
during the ninth clock (acknowledge master). Any number of memory locations can thus be read
one after the other. At address 256, an overflow to address 0 is initiated. With the stop condition, the
data output returns to high-impedance mode. The internal sequence control of the memory
component is reset from the read to the quiescent state with the stop condition.
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