參數(shù)資料
型號(hào): SDA9361
廠商: SIEMENS A G
元件分類: 偏轉(zhuǎn)
英文描述: DDC-PLUS-Deflection Controller
中文描述: HORIZ/VERT DEFLECTION IC, PQFP44
文件頁(yè)數(shù): 6/47頁(yè)
文件大小: 237K
代理商: SDA9361
SDA 9361
Semiconductor Group
6
1998-02-01
Protection against missing V-deflection (CRT-protection)
Selectable softstart of the H-output stage
Clock generation on chip
P-MQFP-44-2 package
5 V supply voltage
1.2
The SDA 9361 is a highly integrated deflection controller for CTV receivers with standard
or doubled line and field frequencies. It controls among others an horizontal driver circuit
for a flyback line output stage, a DC coupled vertical saw-tooth output stage and an east/
west raster correction circuit. All adjustable output parameters are
Ι
2
C Bus controlled.
Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock
system which includes the
Φ
1 and
Φ
2 control loops.
General Description
1.3
Pin Configuration
Figure 1
UEP10278
HSYNC
V
V
V
V
SS(D)
SSD
V
11
1 2 3 4 5 6 7 8 9 10
33
12
44
32 31 30 29 28 27 26 25 24 23
43
13
42
14
41
15
40
16
39
17
38
18
37
19
36
20
35
21
34
22
S
C
X
S
V
D
S
V
X
S
S
R
S
E/W
V
DD(A2)
V
REFP
V
V
ABL
D/A
V
HPROT
REFN
SSA(1)
DDA(1)
C
F
T
H
P
Φ
2
R
V
R
V
V
DD(A3)
V
REFC
SS(A3)
DD(D)
SS(A4)
LF
DD(A4)
VOFFD
V
V
VD+
VD-
V
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