- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄374749 > SDA9361 (SIEMENS A G) DDC-PLUS-Deflection Controller PDF資料下載
參數(shù)資料
| 型號： | SDA9361 |
| 廠商： | SIEMENS A G |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | DDC-PLUS-Deflection Controller |
| 中文描述： | HORIZ/VERT DEFLECTION IC, PQFP44 |
| 文件頁數(shù)： | 12/47頁 |
| 文件大?。?/td> | 237K |
| 代理商： | SDA9361 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁
SDA 9361
Semiconductor Group
12
1998-02-01
2.2
The HSYNC is reference for a numeric PLL. This PLL generates a clock which is phase
locked to the incoming horizontal sync pulse and exactly 864 times faster then the
horizontal frequency. In order to lock the internal frequency to the external sync signal
positive horizontal sync pulses are required (
see figure 4
).
Circuit Description
Figure 4
Incoming Signal HSYNC (CLEXT = 0)
Pulse width
t
w
for
Ι
2
C-Bus Bit ’HSWID’ = 0:
3
μ
s ... 6.1
μ
s
1.5
μ
s ... 3.1
μ
s
Pulse width
t
w
for
Ι
2
C-Bus Bit ’HSWID’ = 1:
3
μ
s ... 8.8
μ
s
1.5
μ
s ... 4.0
μ
s
Rise time
t
r
:100 ns minimum (CLEXT = 0)
low FH-range
high FH-range
low FH-range
high FH-range
The described input signal is first applied to an A/D converter. Conversion takes place
with 6 Bits and a nominal frequency of 27 MHz. The digital PLL uses a low pass filter to
obtain defined slopes for further measurements (PAL/NTSC applications). In addition
the actual high and low level of the signal as well as a threshold value is evaluated and
used to calculate the phase error between internal clock and external horizontal sync
UED10279
r
t
HSmax
V
HSmin
V
V
HSpp
W
t
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| sda 9361 | DDC-PLUS-Deflection Controller(DDC 過偏轉(zhuǎn)控制器) |
| SDA9380-B21 | EDDC Enhanced Deflection Controller and RGB Processor |
| SDA9388X | Single-Chip Picture in Picture IC |
| SDA9400 | Scan Rate Converter using Embedded DRAM Technology Units |
| SDA9410-B13 | Display Processor and Scan Rate Converter using Embedded DRAM Technology Units |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDA9362 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDC-PLUS-Deflection Controller |
| SDA9380 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:EDDC MEGAVISION IC set to support single chip back end solutions for SDTV up to HDTV CRTs |
| SDA9380-B21 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:EDDC Enhanced Deflection Controller and RGB Processor |
| SDA9388X | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Single-Chip Picture in Picture IC |
| SDA9400 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Scan Rate Converter using Embedded DRAM Technology Units |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。