參數(shù)資料
型號(hào)： SDA9290-5
廠商： SIEMENS A G
元件分類： 消費(fèi)家電
英文描述： Picture Processor
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC68
文件頁(yè)數(shù)： 4/22頁(yè)
文件大小： 454K
代理商： SDA9290-5
SDA 9290-5
Semiconductor Group
262
I
2
C Bus Interface
An
I
2
C Bus interface configured as a “slave receiver” is used for programming the different functions
and modes of the picture processor. Via this interface up to four registers can be written according
to the following transfer protocol for controlling the operation mode:
S: Start condition
A: Acknowledge
P: Stop condition
Slave address: 0 0 1 0 1 0 1
(
Note:
There is a general description of the
I
2
C Bus in the Siemens publication “
I
2
C Bus Technical
Description”.)
After every data byte that is transmitted the internal register address (subaddress) is automatically
incremented to the next register so that, if necessary, several registers can be loaded with one
I
2
C
Bus telegram.
In the multi-picture mode the operating mode transmitted on the
I
2
C Bus is switched within the
vertical blanking interval, i.e. during the high phase of signal VS1, if the Memory Sync Controller
(MSC) activates the DREQ line during this period.
It should be noted that the new operating mode has always to be transmitted to the picture
processor first and immediately afterwards to the MSC on the
I
2
C Bus at an interval not longer than
30 ms.
This is the only way to ensure interference-free synchronization of the picture processor and the
MSC. The four
I
2
C Bus registers are described below in more detail. The values marked “*D” in the
right-hand margin are set by an internally generated reset signal (default values) when the
operating voltage is applied.
Register Sub-
address
1)
Data Byte
D7
D6
D5
D4
D3
D2
D1
D0
R0
00
B1
B0
FR
0
SS
VCR
NR
SUV8
R1
01
YF5
YF4
YF3
SL4
SL3
SL2
SL1
SL0
R2
02
0
0
0
SU4
SU3
SU2
SU1
SU0
R3
03
SNTEN SNT1
SNT0
KTEN
KT3
KT2
KT1
KT0
S
0 A
A
A
A P
Slave Address
Sub Address
Data Byte
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