參數(shù)資料
型號: SDA9290-5
廠商: SIEMENS A G
元件分類: 消費家電
英文描述: Picture Processor
中文描述: SPECIALTY CONSUMER CIRCUIT, PQCC68
文件頁數(shù): 10/22頁
文件大?。?/td> 454K
代理商: SDA9290-5
SDA 9290-5
Semiconductor Group
268
Pin Definitions and Functions
Pin
No.
Symbol
Function
Description
1
V
DD
Positive supply
voltage (+ 5 V)
Positive supply voltage (+ 5 V)
2-9
UVQ7 …
UVQ0
Data outputs
Push-pull outputs for directly driving the TV-SAM
chrominance inputs:
8 bits for 4:2:2 format;
4 bits for 4:1:1 format;
[UVQ0 … UVQ3 only valid for 4:2:2 format]
10
V
SS
UVB0 …
UVB7
Ground
Ground (0 V)
11-18
Back-channel data
outputs
Back-channel inputs for chrominance data from TV-SAM
19-26
YB0 …
YB7
Back- channel
data inputs
Back-channel inputs for luminance data from TV-SAM
27-34
UVI0 …
UVI7
Data inputs
Data inputs for chrominance data accept the dig. YUV
signal
35-42
YI0 …
YI7
Data inputs
Data inputs for luminance data accept the dig. YUV
signal
43
DREQ
Data request
signal for multi-
picture mode
Data-request input; initiates data transfer in multi-picture
mode and switches mode together with signal VS1
44
V
SS
BLN
Ground
Ground (0 V)
45
Blanking signal
(15.625 kHz)
Input for line-synchronous blanking signal that
determines line blanking interval (active low) and
synchronizes clock and sequence control
46
LLIN
First system clock
(13.5 or 27 MHz)
Input for line-locked system clock, optionally 13.5 MHz or
27 MHz, from which internal timing is derived. Positive
edge indicates validity of input data
47
LLSEL
Selection of
system clock
frequency (LLIN)
Selection of input clock frequency at pin LLIN for
adapting the IC to the system clock. Low level for
27-MHz clock frequency; high level for 13.5-MHz clock
frequency; no switching inactive mode without picture
interference
48
LL3X
Second system
clock (13.5 MHz)
Input for line-locked 13.5-MHz clock that ensured picture
stability in multi-picture mode and is used as output clock
in every mode
49
SCL
I
2
C Bus shift clock
input
I
2
C Bus shift-clock input
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