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參數(shù)資料
| 型號： | SDA9290-5 |
| 廠商： | SIEMENS A G |
| 元件分類： | 消費家電 |
| 英文描述： | Picture Processor |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 文件頁數(shù)： | 3/22頁 |
| 文件大小： | 454K |
| 代理商： | SDA9290-5 |
SDA 9290-5
Semiconductor Group
261
Multi-Picture Processor
Signals are processed in the 4:1:1 format. The vertical-decimation line memory now operates with
208 (formerly 216) pixels per line to adapt the 1/9th picture format to the new picture memory with
TV-SAMs. Gray frame generation is similarly affected by this change in pixel value.
The signal processing in the decimation filter of the MPP reduces the picture to approximately 1/9th
of its original size. This produces a basis for new features, the full implementation of which calls for
a matching MSC (SDA 9220).
Figure 5
shows how the screen is divided up. The following modes can be implemented with the
MPP:
1. Multi-Picture (automatic)
Fields are extracted from a sequence of movements at fixed intervals, reduced and reproduced
on the screen as a sequence of stills. At one position it is possible to show a moving picture.
2. Multi-Picture (manual)
This differs from the above in that the viewer can determine at the push of a button what phases
of movement are to be stored.
3. Multi-Picture (tuner scanning)
The pictures of the sequence of stills are derived from the different TV channels and give an
overview of the programs on offer. In this mode the picture memory is operated with a crystal-
controlled clock to ensure that the picture remains stable when switching from one channel to
another.
4. Still-in-Picture
A field is extracted from the on-going program, reduced and inserted as a still in the master
channel.
5. Picture-in-Still
The on-going program is inserted as a reduced-size moving picture in a still.
The framing block that follows the decimation filter in the MPP permits frames to be inserted in order
to border the reduced-size pictures on the screen. The brightness of the framing can be varied in
eight steps by the
I
2
C Bus.
The format conversion produced in the demultiplexers for signal processing in the IIP and MPP is
reversed again in the multiplexer MUXO. The picture signal appears again in quasi-parallel format
or parallel format on the output of the MUXO block. The inputs of the TV-SAMs are directly driven
by the sixteen outputs YQ0-YQ7 and UVQ0-UVQ7.
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相關代理商/技術參數(shù) |
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| SDA9290-6 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Picture Processor |
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| SDA9362 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDC-PLUS-Deflection Controller |
| SDA9380 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:EDDC MEGAVISION IC set to support single chip back end solutions for SDTV up to HDTV CRTs |
| SDA9380-B21 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:EDDC Enhanced Deflection Controller and RGB Processor |
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