參數(shù)資料
型號(hào)： SDA9280B22
廠商： SIEMENS A G
元件分類： 消費(fèi)家電
英文描述： ICs for Consumer Electronics
中文描述： SPECIALTY CONSUMER CIRCUIT, PQCC68
文件頁數(shù)： 18/43頁
文件大小： 249K
代理商： SDA9280B22
SDA 9280 B22
Semiconductor Group
18
1998-02-01
The second insertion facility produces a colored background area on the display
controlled by
Ι
2
C Bus. Activating this insertion mode (
Ι
2
C signal: BACKGR) parts of the
display area are covered with a constant color (
Ι
2
C signals: COLBY, COLBU, COLBV).
Starting at a programmable pixel position of each line (
Ι
2
C signal: BCKPOS) the
following part is covered with the background values. The width of the insertion is also
programmable (
Ι
2
C signal: BCKWID). To realize for example two vertical background
stripes at the left and right side of the display BCKPOS should be set to a high value.
Then the background color is inserted over the blanking interval (except the black level
phases) up to the first active pixels of the following line fixed by BCKWID. An example
for application is the display of a 4:3-picture on a 16:9-screen. The free parts of the
display and also the noisy start and end of the picture can be filled with background color.
An opening and closing curtain can also be realized using background insertion mode.
Insertion of an arbitrary pattern is controlled by the external signal INS. The color of the
pattern is programmable (
Ι
2
C signals: COLFY, COLFU, COLFV). The insertion raster
corresponds to the 4:4:4 format. A fixed phase to the video signal is guaranteed by
processing the INS-signal by the compander. Using this insertion mode a colored
framing for multi-picture mode can be realized. The MSC of the Siemens MEGAVISION
System supplies a suited signal (FRM). A connection of the BLN2-signal supplied by the
MSC to the INS-input enables a complete blanking of the horizontal and vertical inactive
parts of the video signal.
The polarity of the INS-signal is programmable by
Ι
2
C Bus (INSNEG).
All insertions are performed after oversampling resulting in sharp transitions without
overshooting.
2.9
Before D/A conversion a fine adjustment of the phase of the luminance signal is
performed (
Ι
2
C signal: YDEL2). The delay of the luminance signal can be varied by one
period of the D/A converter clock.
The amplification factors of each signal component can be reduced by a factor of 0.5
(
Ι
2
C signals: AMPY, AMPU, AMPV). This reduction of nominal amplification reserves
one bit for D/A conversion of overshooting, resulting from strong peaking or interpolation
filtering. The input amplitude resolution of 8 Bit is not reduced. For conversion of signals
without or with only small overshooting a reduction of the amplification factor is not
necessary. A digital limiter circuit prevent the D/A converters from possible overdriving
by clipping.
Note:
Clipping causes a non-linear deformation with interferences between multiples of
the signal frequency and the sample rate of the signal and should be avoided by
reducing the amplification factor.
A triple 9 Bit D/A converter is implemented on the SDA 9280. The DACs are short circuit
protected converters with current outputs.
Amplification, D/A Conversion
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