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參數(shù)資料
| 型號： | SDA9253 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) |
| 中文描述： | VIDEO DRAM, PQFP64 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 174K |
| 代理商： | SDA9253 |
SDA 9253
Semiconductor Group
4
1998-01-30
Data Transfer from Latch B to Shift Register B (RB)
The contents of latch B are transferred to shift register B at the falling edge of the read transfer
signal RB. If the timing restrictions between RB and the shift clock SCB are taken into account, a
continuous data flow at output SQB without interrupts is possible. This transfer operation is
independent on all other transfer operations except for a small forbidden time window conditioned
by the memory to latch B transfer.
Data Output A (SQA, SCA, OEA)
Data is shifted out through the serial port A (SQA0 … SQA11) at the rising edge of the shift clock
SCA. After 16 clock cycles new data have to be transferred from latch A to shift register A.
Otherwise data values are cyclically repeated.
Via the output enable OEA the output buffers can be switched into tristate.
The shift clock SCA may be completely independent on the shift clock for port B and C (SCB).
Data Output B (SQB, SCB, OEB)
Data is shifted out through the serial port B (SQB0 … SQB11) at the rising edge of the shift clock
SCB. After 16 clock cycles new data have to be transferred from latch B to shift register B.
Otherwise data values are cyclically repeated. The shift clock SCB is also used for the input port C.
Via the output enable OEB the output buffers can be switched into tristate.
Refresh
Either 256 refresh cycles or read/write cycles on 212 consecutive row addresses beginning with
address 0 have to be executed within an 16 ms interval to maintain the data in the memory arrays.
A refresh cycle is determined by the mode control bits, see “Addressing and Mode Control”. In the
refresh mode, the row and column addresses are ignored.
Initialization
The device incorporates an on-chip substrate bias generator as well as dynamic circuitry. Therefore
an initial pause of 200
μ
s is required after power on, followed by eight RE-cycles before proper
device operation is achieved.
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| SDA9254-2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) with On-chip Noise Reduction Filter |
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| SDA9257 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Clock Sync Generator |
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| SDA9280 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:ICs for Consumer Electronics |
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