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參數(shù)資料
| 型號： | SDA9253 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 2.6 MBit Dynamic Sequential Access Memory for Television Applications (TV-SAM) |
| 中文描述： | VIDEO DRAM, PQFP64 |
| 文件頁數(shù)： | 13/25頁 |
| 文件大?。?/td> | 174K |
| 代理商： | SDA9253 |
SDA 9253
Semiconductor Group
13
1998-01-30
WT to RE lead time
t
WRL
30
ns
t
WRL
and
t
RWL
are restrictive
operating parameters only
in memory write transfer
cycles. In that case
t
WRL
applies if the write transfer
from shifter C to latch C
occurs before the rising
edge of RE. Otherwise
t
RWL
has to be satisfied.
See diagram 4
RE to WT lead time
t
RWL
t
OFF
50
ns
See WT to RE lead time
t
OFF
(max) defines the time
at which the output
achieves the open-circuit
condition and is not
referenced to output
voltages levels.
Output buffer turn-
off delay
0
20
ns
WT to SCB delay
time
t
WTD
0
ns
See diagram 4
WT to SCB lead
time
t
WTL
15
ns
See diagram 4
WT pulse width
t
WTP
t
OAA
10
ns
See diagram 4
OEA to output A
access time
25
ns
See diagram 2, 5
OEB to output B
access time
t
OBA
25
ns
See diagram 3, 5
Access time from
SCA
t
CAA
25
ns
See diagram 2
Access time from
SCB
t
CBA
25
ns
See diagram 3
Data input set-up
time to SCB
t
DS
5
ns
See diagram 5
Data input hold time
to SCB
t
DH
6
ns
See diagram 5
AC Characteristics
(cont’d)
V
DD
= 5 V
±
10 %;
T
A
= 0 to 70
°
C
Parameter
Symbol
Limit Values
Unit
Test Condition
min.
typ.
max.
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