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參數(shù)資料
| 型號： | SDA9187-3X |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | ADC |
| 英文描述： | TRIPLE 1-CH 6-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, DSO-28 |
| 文件頁數(shù)： | 6/25頁 |
| 文件大小： | 111K |
| 代理商： | SDA9187-3X |
Semiconductor Group
14
SDA 9187-3X
Design of the Loop Filter Network
For the calculation of the control response the following formulas can be applied.
Characteristic circuit frequency:
loop bandwidth
ω
0 = (K/C1)
0.5
damping factor
ζ = 0.5 × R × (K × C
1)
0.5
K = 0.52 typical
K = 0.75 maximum
The parallel capacitanceC2 should not exceed 5 % ofC1.
Because of the discrete detection of the phase differences every 64
s, phase modulation of half the
line frequency is superimposed on the transient response of the PLL. To make sure that this phase
modulation is damped sufficiently.
1.74 > R1
× 47 × 10 – 6 × 1/ × (1 – 2 / (1 + eα))
with
a = 64
s. / (R
1
× C
2)
or approx. by
R1
× C
2 << 64
s
1.74 > R1 × 47 × 10 – 6 × 1/
For the board layout it is important to
a) block supply lines near the supply pins,
b) keep the wiring of C2 short.
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