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參數(shù)資料
| 型號： | SDA9187-3X |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | ADC |
| 英文描述： | TRIPLE 1-CH 6-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, DSO-28 |
| 文件頁數(shù)： | 12/25頁 |
| 文件大?。?/td> | 111K |
| 代理商： | SDA9187-3X |
Semiconductor Group
2
The luminance signal Y and the chrominance signals U, V are fed to the SDA 9187-3X by means
of coupling capacitors. The color subcarrier must be filtered out of Y.
The sampling rate of the three 6-bit A/D-flash converters is the LL3 clock.
The dynamic range of the converter is the range between
VREFH and VREFL.
The black level of Y is clamped toVREFL.
The luminance information is generated as a 6-bit binary offset code. The digitized luminance signal
Y can be delayed to compensate the different signal propagation times of the preceding decoder.
This delay can be set in increments of two LL3 cycles in a range of 0 through 15 LL3 cycles
(nominally 0 to 1.11
s) on pins YD0, YD1 and YD2.
U and V is clamped to 0.5
× (V
REFH + VREFL). U, V are then converted into a 6-bit two’
s complement
code.
The digitized U-, V-signals can be inverted via the CNEG-control input. A multiplexer selects every
fourth U-, V-sample and applies this 12-bit information in four clock cycles in a nibble format to pins
UV (0:3).
The horizontal PLL, consisting of a horizontal timer, phase comparator and VCO, generates the
line-locked picture-in-picture system clock LL3 and the internal chip timing. The PLL is designed to
operate both in the single-ended mode and - for improved performance - in a differential PLL-mode.
The horizontal timer divides the LL3-clock by 864 (the same for PAL and NTSC) and applies this
signal as a horizontal reference signal to the phase comparator. The external horizontal signal is
decoded from the sandcastle signal and matched in its pulse width (= 345 LL3-cycles) to the
reference signal. The digital phase comparator is frequency- and phase-sensitive and produces
current pulses at its output. The up/down pulses of the phase comparator are filtered on pin RC. The
filtered signal is the control voltage of the VCO. The horizontal timer also determines the start time
and the width of the clamping pulse as well as the location of the blanking signal BLN, which in turn
defines the horizontal duration of the picture information on the Y output and should be synchronous
with it. BLN is consequently delayed to the same degree as Y.
Clamping
An internal clamping circuit is provided in each of the three analog channels.
The external clamping capacitance is loaded by on chip current sources during clamping
(typ. 100
A). So the loading time depends on the values of the ext. clamping capacitor.
SDA 9187-3X
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SDA9188-3X | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Picture-in-Picture Processor with On-Chip PLL |
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| SDA9189X-A132 | 制造商:Siemens 功能描述:Part Number Only |
| SDA9205-2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Triple 8-Bit Analog-to-Digital-Converter |
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