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參數(shù)資料
| 型號： | SDA9187-3X |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | ADC |
| 英文描述： | TRIPLE 1-CH 6-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封裝： | 0.300 INCH, PLASTIC, DSO-28 |
| 文件頁數(shù)： | 4/25頁 |
| 文件大?。?/td> | 111K |
| 代理商： | SDA9187-3X |
Semiconductor Group
12
SDA 9187-3X
Clamping
For each analog channel there is an internal clamping circuit.
Analog inputs YIN, UIN and VIN are pulled to internally generated clamping levels. The clamping
signals necessary for this are also generated internally (
see Clamping Pulse Timing Diagram).
The external clamping capacitor is charged to the appropriate clamping level every line for 42 CLK
cycles by internal current sources.
Clamping levels:
Analog signal
Binary Code
YIN
0 0 0 0 0 0
UIN, VIN
1 0 0 0 0 0
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