參數(shù)資料
型號(hào): sda 9361
廠商: SIEMENS AG
英文描述: DDC-PLUS-Deflection Controller(DDC 過偏轉(zhuǎn)控制器)
中文描述: DDC的加偏轉(zhuǎn)控制器(DDC的過偏轉(zhuǎn)控制器)
文件頁(yè)數(shù): 7/47頁(yè)
文件大?。?/td> 237K
代理商: SDA 9361
SDA 9361
Semiconductor Group
7
1998-02-01
1.4
Pin Description
Pin No. Symbol
1
2
3
4
5
6
7
8
Type
I/TTL
I
Q
IQ
I
I/TTL
Q/TTL
Q
Description
Input for external clock
Reference oscillator input, crystal
Reference oscillator output, crystal
Ι
2
C-Bus data
Ι
2
C-Bus clock
Reset input, active low
Control signal for vertical positioning of OSD, PIP etc.
Blanking signal with H- and color burst component
(V-component selectable by
Ι
2
C Bus)
Digital supply
Digital ground
Watching external V-output stage (input is the V-saw-
tooth from feedback resistor)
Watching EHT (input is e.g. H-flyback)
Analog supply
Output of an
Ι
2
C Bus controlled DC voltage
Input for a beam current dependent signal for
stabilization of width, height and H-phase
Analog ground
Ground for
V
REFP
,
V
REFH
,
V
REFL
Reference voltage for IBEAM ADC, DAC, HPROT /
VPROT thresholds
Analog supply
Control signal output for east/west raster correction
Control signal output for DC coupled V-output stage
Like VD+
Analog ground
Reference voltages for E/W-DAC, V-DAC
Like
V
REFL
Line flyback for H-delay compensation
Control signal output
CLKI
X1
X2
SDAT
SCLK
RESN
SCAN
SCP
9
10
11
V
DD(D)
V
SS(D)
VPROT
S
S
I
12
13
14
15
HPROT
V
DD(A1)
D/A
ABL
I
S
Q
I
16
17
18
V
SS(A1)
V
REFN
V
REFP
S
IQ
IQ
19
20
21
22
23
24
25
26
27
V
DD(A2)
E/W
VD+
VD-
V
SS(A2)
V
REFL
V
REFH
Φ
2
PWM
S
Q
Q
Q
S
IQ
IQ
I
Q/TTL
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