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參數(shù)資料
| 型號： | sda 9361 |
| 廠商： | SIEMENS AG |
| 英文描述： | DDC-PLUS-Deflection Controller(DDC 過偏轉(zhuǎn)控制器) |
| 中文描述： | DDC的加偏轉(zhuǎn)控制器（DDC的過偏轉(zhuǎn)控制器） |
| 文件頁數(shù)： | 14/47頁 |
| 文件大?。?/td> | 237K |
| 代理商： | SDA 9361 |
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SDA 9361
Semiconductor Group
14
1998-02-01
2.3
The circuit is completely reset at power-on/off (
timing diagram see figure 11
) or if the
pin RESN has L-level (
timing diagram see figure 12
). During standby operation some
parts of the circuit are not affected (
timing diagram see figure 12
):
Reset Modes
Note:
Power-On-Reset and RESN = Low state are deactivated after ca. 32 cycles of the
X1/X2 oscillator clock and ca. 42 cycles of the CLL clock.
Standby state is deactivated after ca. 42 cycles of the CLL clock.
1)
Can only be read after Power-On-Reset is finished
Power-On-Reset
External Reset
(pin RESN = Low)
Low
Inactive
Inactive
Tristate
Standby Mode
(
I
2
C Bit STDBY = 1)
Active
Inactive
Inactive
Ready
HD output
H-protection
V-protection
Ι
2
C interface (SDA,
SCL)
Ι
2
C register
01
H
...1C
H
, 1F
H
Ι
2
C register 00
H
,
1D
H
, 1E
H
, 44
H
...48
H
Status Bit PONRES
V
REFP
,
V
REFH
.
V
REFL
CPU
Low
Inactive
Inactive
Tristate
Set to default values Set to default values Set to default values
Set to default values Set to default values Not affected
Set to 1
1)
Not affected
Inactive
Set to 1
1)
Not affected
Inactive
Not affected
Inactive
Inactive
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDA9362 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:DDC-PLUS-Deflection Controller |
| SDA9380 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:EDDC MEGAVISION IC set to support single chip back end solutions for SDTV up to HDTV CRTs |
| SDA9380-B21 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:EDDC Enhanced Deflection Controller and RGB Processor |
| SDA9388X | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Single-Chip Picture in Picture IC |
| SDA9400 | 制造商:MICRONAS 制造商全稱:MICRONAS 功能描述:Scan Rate Converter using Embedded DRAM Technology Units |
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