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參數(shù)資料
| 型號(hào)： | sda 9361 |
| 廠商： | SIEMENS AG |
| 英文描述： | DDC-PLUS-Deflection Controller(DDC 過(guò)偏轉(zhuǎn)控制器) |
| 中文描述： | DDC的加偏轉(zhuǎn)控制器（DDC的過(guò)偏轉(zhuǎn)控制器） |
| 文件頁(yè)數(shù)： | 11/47頁(yè) |
| 文件大?。?/td> | 237K |
| 代理商： | SDA 9361 |
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SDA 9361
Semiconductor Group
11
1998-02-01
VPROT:
Vertical saw-tooth voltage
V
i
< V1 in first half of V-period or
V
i
> V2 in second half: HD disabled
The pin SCP delivers the composite blanking signal SCP. It contains burst (
V
b
), H-
blanking HBL (
V
HBL
) and selectable V-blanking (control bit SSC). The phase and width
of the H-blanking period can be varied by
Ι
2
C Bus. For the timing following settings are
possible:
BD = 1
BD = 0, BSE = 0 (default value)
BD = 0, BSE = 1(alignment range)
:
t
BL
= 0
:
t
HBL
=
t
f
(H-flyback time)
:
t
HBL
= (4
*
H-blanking-time + 1) / CLL
:
t
DBL
= (H-shift + 4
*
H-blanking-phase
-2
*
H-blanking-time + 43) / CLL
:
t
BL
=
t
VBL
during V-blanking period
:
t
BL
is always
t
HBL
SSC = 0
SSC = 1
Figure 3
BG-pulse width
t
B
Delay to HSYNC
t
DB
54 / CLL
if CLEXT = L-level: (76-4
*
Internal-H-sync-phase) / CLL
if CLEXT = H-level:
(38-4
*
Internal-H-sync-phase) / CLL
UED10260
Input Signal
HSYNC
B
t
DB
t
DBL
t
t
BL
OH
V
OHBL
V
OL
V
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| SDA9362 | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:DDC-PLUS-Deflection Controller |
| SDA9380 | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:EDDC MEGAVISION IC set to support single chip back end solutions for SDTV up to HDTV CRTs |
| SDA9380-B21 | 制造商:MICRONAS 制造商全稱(chēng):MICRONAS 功能描述:EDDC Enhanced Deflection Controller and RGB Processor |
| SDA9388X | 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:Single-Chip Picture in Picture IC |
| SDA9400 | 制造商:MICRONAS 制造商全稱(chēng):MICRONAS 功能描述:Scan Rate Converter using Embedded DRAM Technology Units |
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