參數(shù)資料
型號(hào): sda 9205
廠商: SIEMENS AG
英文描述: Triple 8-Bit Analog-to-Digital-Converter(三倍8位A/D轉(zhuǎn)換器)
中文描述: 三8位模擬到數(shù)字轉(zhuǎn)換器(三倍8位的A / D轉(zhuǎn)換器)
文件頁數(shù): 8/31頁
文件大小: 560K
代理商: SDA 9205
SDA 9205-2
Semiconductor Group
8
The following DSP functions are available
Averaged results are rounded to eight bits (X
0.5
0; X > 0.5
1)
A group delay of 0.5 CLK cycles exists between DSP (1.0, 2.0) and the other DSP functions.
(1.0)
α
n
= a
n – 3
α
n
= 1/2 (a
n – 4
+ a
n – 3
)
ADC A
(1.1)
n = sampling point
(2.0)
β
n
= b
n – 3
β
n
= 1/2 (b
n – 4
+ b
n – 3
)
β
4n
= 1/4 (b
4n – 5
+ b
4n – 4
+ b
4n – 3
+ b
4n – 2n
),
β
4n – 3,2,1
β
8n
= 1/8 (b
8n – 7
+ b
8n – 6
+ ..... + b
8n
),
ADC B
(2.1)
(2.2)
arbitrarily
(2.3)
β
8n – 7,6,5,4,3,2,1
arbitrarily
(2.0)
γ
n
= c
n – 3
γ
n
= 1/2 (c
n – 4
+ c
n – 3
)
γ
4n
= 1/4 (c
4n – 5
+ c
4n – 4
+ c
4n – 3
+ c
4n – 2
)
γ
8n
= 1/8 (c
8n – 7
+ c
8n – 6
+ ..... + c
8n
)
ADC C
(2.1)
(2.2)
γ
4n – 3,2,1
γ
8n – 7,6,5,4,3,2,1
arbitrarily
(2.3)
arbitrarily
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